Cirrus Logic CS2100-CP - Manual (Page 3)

CS2100-CP
DS840F2 3
8.4.2 Enable Device Configuration Registers 2 (EnDevCfg2) ....................................................... 28
8.5 Ratio (Address 06h - 09h) .............................................................................................................. 28
8.6 Function Configuration 1 (Address 16h) ........................................................................................ 29
8.6.1 Clock Skip Enable (ClkSkipEn) ............................................................................................. 29
8.6.2 AUX PLL Lock Output Configuration (AuxLockCfg) .............................................................. 29
8.6.3 Reference Clock Input Divider (RefClkDiv[1:0]) .................................................................... 29
8.7 Function Configuration 2 (Address 17h) ........................................................................................ 30
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl) ................................................................. 30
8.7.2 Low-Frequency Ratio Configuration (LFRatioCfg) ................................................................ 30
8.8 Function Configuration 3 (Address 1Eh) ........................................................................................ 30
8.8.1 Clock Input Bandwidth (ClkIn_BW[2:0]) ................................................................................ 30
9. CALCULATING THE USER DEFINED RATIO .................................................................................... 31
9.1 High Resolution 12.20 Format ....................................................................................................... 31
9.2 High Multiplication 20.12 Format ................................................................................................... 31
10. PACKAGE DIMENSIONS .................................................................................................................. 32
THERMAL CHARACTERISTICS ......................................................................................................... 32
11. ORDERING INFORMATION .............................................................................................................. 33
12. REFERENCES .................................................................................................................................... 33
13. REVISION HISTORY .......................................................................................................................... 34
LIST OF FIGURES
Figure 1. Typical Connection Diagram ........................................................................................................ 6
Figure 2. CLK_IN Sinusoidal Jitter Tolerance ............................................................................................. 9
Figure 3. CLK_IN Sinusoidal Jitter Transfer ................................................................................................ 9
Figure 4. CLK_IN Random Jitter Rejection and Tolerance ......................................................................... 9
Figure 5. Control Port Timing - I²C Format ................................................................................................ 10
Figure 6. Control Port Timing - SPI Format (Write Only) .......................................................................... 11
Figure 7. Delta-Sigma Fractional-N Frequency Synthesizer ..................................................................... 12
Figure 8. Hybrid Analog-Digital PLL .......................................................................................................... 13
Figure 9. Internal Timing Reference Clock Divider ................................................................................... 14
Figure 10. REF_CLK Frequency vs. a Fixed CLK_OUT ........................................................................... 14
Figure 11. External Component Requirements for Crystal Circuit ............................................................ 15
Figure 12. CLK_IN removed for > 2
23
SysClk cycles ................................................................................ 16
Figure 13. CLK_IN removed for < 2
23
SysClk cycles but > t
CS .................................................................................. 16
Figure 14. CLK_IN removed for < t
CS .................................................................................................................................. 17
Figure 15. Low bandwidth and new clock domain .................................................................................... 18
Figure 16. High bandwidth with CLK_IN domain re-use ........................................................................... 18
Figure 17. Ratio Feature Summary ........................................................................................................... 20
Figure 18. PLL Clock Output Options ....................................................................................................... 21
Figure 19. Auxiliary Output Selection ........................................................................................................ 21
Figure 20. Control Port Timing in SPI Mode ............................................................................................. 23
Figure 21. Control Port Timing, I²C Write .................................................................................................. 24
Figure 22. Control Port Timing, I²C Aborted Write + Read ....................................................................... 24
LIST OF TABLES
Table 1. Ratio Modifier .............................................................................................................................. 19
Table 2. Example 12.20 R-Values ............................................................................................................ 31
Table 3. Example 20.12 R-Values ............................................................................................................ 31