Cirrus Logic CS2200-CP - Manual (Page 10)

CS2200-CP
10 DS759F2
4. ARCHITECTURE OVERVIEW
4.1 Delta-Sigma Fractional-N Frequency Synthesizer
The core of the CS2200 is a Delta-Sigma Fractional-N Frequency Synthesizer which has very high-resolu-
tion for Input/Output clock ratios, low phase noise, very wide range of output frequencies and the ability to
quickly tune to a new frequency. In very simplistic terms, the Fractional-N Frequency Synthesizer multiplies
the Timing Reference Clock by the value of N to generate the PLL output clock. The desired output to input
clock ratio is the value of N that is applied to the delta-sigma modulator (see
Figure 4 ).
The analog PLL based frequency synthesizer uses a low-jitter timing reference clock as a time and phase
reference for the internal voltage controlled oscillator (VCO). The phase comparator compares the fraction-
al-N divided clock with the original timing reference and generates a control signal. The control signal is fil-
tered by the internal loop filter to generate the VCO’s control voltage which sets its output frequency. The
delta-sigma modulator modulates the loop integer divide ratio to get the desired fractional ratio between the
reference clock and the VCO output (thus the one’s density of the modulator sets the fractional value). This
allows the design to be optimized for very fast lock times for a wide range of output frequencies without the
need for external filter components. As with any Fractional-N Frequency Synthesizer the timing reference
clock should be stable and jitter-free.
Figure 4. Delta-Sigma Fractional-N Frequency Synthesizer
Fractional-N
Divider
Timing Reference
Clock
PLL Output
Voltage Controlled
Oscillator
Internal
Loop Filter
Phase
Comparator
N
Delta-Sigma
Modulator