Cirrus Logic CS2200-CP - Manual (Page 22)

CS2200-CP
22 DS759F2
8.6 Function Configuration 1 (Address 16h)
8.6.1 AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.6.2 Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
8.7 Function Configuration 2 (Address 17h)
8.7.1 Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
7 6 5 4 3 2 1 0
Reserved AuxLockCfg Reserved RefClkDiv1 RefClkDiv0 Reserved Reserved Reserved
AuxLockCfg AUX_OUT Driver Configuration
0 Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
1 Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
Application: “Auxiliary Output” on page 15
RefClkDiv[1:0] Reference Clock Input Divider REF_CLK Frequency Range
00 ÷ 4. 32 MHz to 56 MHz (50 MHz with XTI)
01 ÷ 2. 16 MHz to 28 MHz
10 ÷ 1. 8 MHz to 14 MHz
11 Reserved.
Application: “Internal Timing Reference Clock Divider” on page 11
7 6 5 4 3 2 1 0
Reserved Reserved Reserved ClkOutUnl Reserved Reserved Reserved Reserved
ClkOutUnl Clock Output Enable Status
0 Clock outputs are driven ‘low’ when PLL is unlocked.
1 Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
Application: “PLL Clock Output” on page 14