Cirrus Logic CS35L32 - Manual (Page 29)

DS963F4 29
CS35L32
4.13 Device Clocking
4.13 Device Clocking
The device can operate as a clock master, creating both SCLK and LRCK for itself and for other devices in the system. It
can also be operated as a clock slave, receiving the SCLK and LRCK signals as input. In either case, internal controls are
used to advise (in Slave Mode) or set (in Master Mode) the clocking relationships among the externally applied MCLK, the
internally derived MCLK (MCLK
INT
), SCLK, and LRCK.
4.13.1 Internal Master Clock Generation
An internal clock (MCLK
INT
) is derived from the clocking signal that drives the MCLK pin. The user must configure
MCLKDIV2 (see p. 37 ) so the proper internal MCLK signal can be derived. When the external clock is 6 or 6.144 MHz,
MCLK
INT
can simply be a buffered version of the clock that drives the MCLK pin. This is done by clearing MCLKDIV2.
However, if the external clock is 12 or 12.288 MHz, it must be halved to achieve an MCLK
INT
rate of approximately 6 MHz.
This is done by setting MCLKDIV2.
Table 4-14 outlines the supported internal MCLK
INT
nominal frequency and how it is derived from the supported
frequencies of the external MCLK source (MCLK input pin).
To save power, MCLK can be disabled by setting MCLKDIS (see p. 37 ).
4.13.2 ADSP Device Clocking
The CS35L32 can operate as a clock master, creating both SCLK and LRCK for itself and for other system devices. It can
also operate as a clock slave, receiving SCLK and LRCK signals as inputs. In Master Mode, CS35L32 determines clocking
relationships among SCLK, LRCK, and the externally applied MCLK.
Table 4-13. SDOUT Monitor Data Positioning (Two CS35L32s, DATCNF = 11)
Bit Bit Number Left Channel Data Contents Right Channel Data Contents
MSB 1 VPMON[7] Device 0 VPMON[7] Device 1
MSB – 1 2 VPMON[6] Device 0 VPMON[6] Device 1
… … … …
MSB – 7 8 VPMON[0] Device 0 VPMON[0] Device 1
MSB – 8 9 AMP_SHORT Device 0 AMP_SHORT Device 1
MSB – 9 10 OTW Device 0 OTW Device 1
MSB – 10 11 OTE Device 0 OTE Device 1
MSB – 11 12 VMONIMON_OVFL Device 0 VMONIMON_OVFL Device 1
MSB – 12 13 VPMON_OVFL Device 0 VPMON_OVFL Device 1
MSB – 13 14 PDN_DONE Device 0 PDN_DONE Device 1
MSB – 14 15 BOOST_CURLIM Device 0 BOOST_CURLIM Device 1
MSB – 15 16 LED_TIMERON Device 0 LED_TIMERON Device 1
MSB – 16 17 VMON_OVFL Device 0 VMON_OVFL Device 1
MSB – 17 18 IMON_OVFL Device 0 IMON_OVFL Device 1
MSB – 18 19 UVLO Device 0 UVLO Device 1
MSB – 19 20 BOOST_OVERROR Device 0 BOOST_OVERROR Device 1
MSB – 20 21 LED12_FLEV Device 0 LED12_FLEV Device 1
MSB – 21 22 LED12_MVEV Device 0 LED12_MVEV Device 1
MSB – 22 to MSB – 31 23–32 Reserved Reserved
Table 4-14. Internal Master Clock Generation
MCLK Rate (MHz) Required Divide Ratio MCLK
INT
Rate (MHz) Settings for MCLKDIV2
6.0000 1 6.0000 0
12.0000 2 1
6.1440 1 6.1440 0
12.2880 2 1