Cirrus Logic CS35L32 - Manual (Page 30)

30 DS963F4
CS35L32
4.14 Control Port Operation
4.13.3 Error Conditions
MCLK, SCLK, and LRCK are monitored for clocking and configuration errors. If an MCLK or ADSP error occurs, the
respective MCLK_ERR or ADSPCLK_ERR bit is set, and, if the respective mask bit is cleared, INT is asserted.
• MCLK error (MCLK_ERR). If MCLK were to stop abruptly while the boost converter or amplifier’s output stages are
switching, it could damage or destroy the device. Because of this, the CS35L32 integrates a watchdog circuit to
monitor MCLK frequency. To prevent damage, if MCLK is removed or drops below ~1.25 MHz, the boost converter
is placed in Bypass Mode and audio and LED operations are shut down. The Class D amplifier immediately stops
switching and both outputs are internally clamped to ground. After such a disturbance, once a proper MCLK can be
applied, the device should be reset to ensure recovery to a known state.
Whenever the MCLK watchdog determines that MCLK is too slow, the event is recorded in
MCLK_ERR (see p. 41 ).
If MCLK_ERR is set, the device must be reset (RESET = HIGH LOW), released from reset (RESET = LOW 
HIGH) once a valid MCLK is reapplied, and then restarted adhering to the specifications in Table 3-11 . Once
restarted, default audio functionality resumes with the boost converter in Bypass Mode. Registers must be reloaded,
since the RESET operation will have cleared them.
• ADSPCLK error (ADSPCLK_ERR). If the ADSP RATIO is not configured properly for the MCLK and audio clocks
supplied to the CS35L32, an ADSP error is triggered ( ADSPCLK_ERR = 1, see p. 41 ). Section 4.11.2 describes
ADSPCLK_ERR and how to configure the ADSP.
The CS35L32 monitors the MCLK
INT
-to-LRCK ratio to determine whether it is valid according to the RATIO setting
(see p. 37 ). If it is invalid, an ADSPCLK_ERR error occurs and, if M_ADSPCLK_ERR = 0, INT is asserted.
While the ADSP is attempting to correlate the incoming clocks to the settings of the ratio controls, the state machine
may flag the error condition several times, causing multiple assertions of the INT pin. To avoid this, the mask bit for
this error can be set after the initial notice, followed by the actions from a service routine to clear the error, and then
clearing the mask bit once the service routine has run.
This error is cleared automatically when the ratio matches the control port settings.
4.14 Control Port Operation
The control port is used to access the registers allowing the amplifier and LED drivers to be configured for the desired
operational modes and formats. Control port operation can be asynchronous with respect to the audio sample rates.
However, to avoid potential interference problems, the control-port pins should remain static if no operation is required.
The control port operates using an I²C interface with the amplifier acting as a slave device. Device communication should
not begin until the reset and power-up timing requirements specified in
Table 3-11 and Table 3-13 are met.
Note: The VA and VP supplies are needed for proper control-port operation. Additionally, although registers can be
written to and read from while MCLK is powered down, a valid MCLK is required to advance the state machines
affected by register settings.
4.14.1 I²C Interface and Protocol
The serial control-port data pin, SDA, is a bidirectional data line. Data is clocked into and out of the CS35L32 by the I²C
clock, SCL. The signal timings for read and write cycles are shown in
Fig. 4-11 – Fig. 4-13 . A start condition is defined as
a falling transition of SDA while the clock is high. A stop condition is defined as a rising transition of SDA while the clock
is high. All other SDA transitions occur while the clock is low.
The first byte sent to the CS35L32 after a start condition consists of a 7-bit chip address field and a R/W bit (high for a
read, low for a write) in the LSB. To communicate with the CS35L32, the I
2 C slave address, shown in Fig. 4-11 , should
match 100 0000 if the AD0 pin is at level 0, and should match 100 0001 if it is at level 1.