16 interrupt mask 1, 17 interrupt mask 2, Interrupt mask 1 – Cirrus Logic CS35L32 User Manual
Page 40: Section 7.16, Interrupt mask 2, Section 7.17, M_amp_short p. 40, M_ote p. 40, Ote_rls p. 40, M_otw
40
DS963F4
CS35L32
7.16 Interrupt Mask 1
0
OTE_
RLS
Overtemperature error protection release. Releases (removes) OTE-caused Speaker-Safe Mode if the OTE condition is no
longer present, which can be determined by reading
) twice.
0 (Default)
1
0
1 0 sequence
If the OTE condition is present, Speaker-Safe Mode is applied.
At the end of the sequence, if the OTE condition is no longer present, the Speaker-Safe Mode is
cleared, unless an amplifier short cause is still active.
Note: For these bits, if the condition that causes automatic protection becomes true again during the protection potential release sequence
(x_RLS: 0
1 0), protection is not removed, the related interrupt status bit is set again, and, if unmasked, a new interrupt is generated.
7.16 Interrupt Mask 1
Address 0x12
R/W
7
6
5
4
3
2
1
0
—
M_ADSPCLK_ERR M_MCLK_ERR M_AMP_SHORT
M_OTW
M_OTE
Default
1
1
1
1
1
1
1
1
Interrupt mask register bits serve as a mask for the interrupt sources in the interrupt status registers. Interrupts are described in
.
Bits
Name
Description
7:5
—
Reserved
4
M_ADSPCLK_ERR Error masks
0 Unmasked
1 (Default) Masked
3
M_MCLK_ERR
2
M_AMP_SHORT AMP_SHORT mask
0 Unmasked
1 (Default) Masked
1
M_OTW
OTW mask
0 Unmasked
1 (Default) Masked
0
M_OTE
OTE mask
0 Unmasked
1 (Default) Masked
7.17 Interrupt Mask 2
Address 0x13
R/W
7
6
5
4
3
2
1
0
M_VMON_OVFL M_IMON_OVFL M_VPMON_OVFL
—
M_PDN_DONE
Default
1
1
1
1
1
1
1
1
Interrupt mask register bits serve as a mask for the interrupt sources in the interrupt status registers. Interrupts are described in
.
Bits
Name
Description
7
M_VMON_OVFL
Overflow masks
0 Unmasked
1 (Default) Masked
6
M_IMON_OVFL
5
M_VPMON_OVFL
4:1
—
Reserved
0
M_PDN_DONE
PDN_DONE mask
0 Unmasked
1 (Default) Masked
Bits
Name
Description