Cirrus Logic CS35L32 - Manual (Page 32)

32 DS963F4
CS35L32
5 Applications
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10000001 (chip address and read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Note: For I 2 C reads, the interrupt status registers and the register at the address that precedes an interrupt status
register must be read individually and not as a part of an autoincremented control-port read. An autoincremented
read of any of these registers may clear the contents of an interrupt status register and return invalid interrupt
status data. As a result, if an unmasked interrupt condition had caused the INT pin to be asserted, the
autoincremented read that prematurely clears the corresponding interrupt status bit causes INT to be deasserted.
Therefore, to avoid affecting interrupt status register contents, interrupt status registers and the register at the
preceding address (specifically, registers at addresses 0x14–0x17) must only be read individually.
5 Applications
5.1 Required Reserved Register Configuration
The following initialization sequence must be written after the release of reset but before power down bit is cleared:
• Write register 0x00 with the value 0x99.
• Write register 0x43 with the value 0x01.
• Write register 0x00 with the value 0x00.
To address the issue where a small dip can be seen in the audio output signal as the amplifier enters clipping, the following
I
2 C sequence must be written at initialization:
• Write register 0x00 with the value 0x99.
• Write register 0x3B with the value 0x62.
• Write register 0x3C with the value 0x80.
• Write register 0x00 with the value 0x00.
To address the issue where spurious tones exists on both the IMON/VMON ADCs during idle channel conditions, the
following I
2 C sequence must be written at initialization to reduce the amplitude of these tones:
• Write register 0x00 with the value 0x99.
• Write register 0x24 with the value 0x40.
• Write register 0x00 with the value 0x00.
By default, the boost converter output is incorrect if VP exceeds 3.7 V. When a boost event is requested in this condition,
the boost converter output is 5.8 V instead of the nominal 5 V.
The following I 2 C sequence must be written at initialization to correct this behavior:
• Write register 0x00 with the value 0x99.
• Write register 0x49 with the value 0x56.
• Write register 0x00 with the value 0x00.
5.2 Avoiding Current Transients when Issuing a Flash Event
When the boost converter is configured in either of the two automatic managed modes (VBOOST_MNG = 00 or VBOOST_
MNG = 01) and a flash LED event is indicated, a current transient can be seen at the output of the boost converter (VBST)
through FLOUTx whenever a voltage boost is requested. The duration of this transient is approximately 200
 Did not
update. A current transient is also observed in the current that sources VP. The LED current settles to the programmed
value in the LED_FLCUR field after the current transient.