Fpga register description, 1 tdm conversion (address 01h), 2 codec sdin control (address 02h) – Cirrus Logic CDB42438 User Manual

Page 16: Table 1. data to sdin, P 16

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Fpga register description, 1 tdm conversion (address 01h), 2 codec sdin control (address 02h) | Table 1. data to sdin, P 16 | Cirrus Logic CDB42438 User Manual | Page 16 / 51 Fpga register description, 1 tdm conversion (address 01h), 2 codec sdin control (address 02h) | Table 1. data to sdin, P 16 | Cirrus Logic CDB42438 User Manual | Page 16 / 51
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