Cirrus Logic CDB42438 - Manual (Page 29)

CDB42438
DS646DB2 29
8. CDB BLOCK DIAGRAM
CS42438
CS8416 S/PDIF
Inpu
t
y
D
iffer
ential
to
Si
ngl
e-Ende
d
Ou
tput
y
Si
ngl
e-Ende
d
Ou
tput
y
Si
ngl
e-Ende
d to
D
iffer
enti
a
l In
put
y
Si
ngl
e-Ende
d
Input
S
e
ria
l Con
trol
Po
rt
FPGA
CS8406 S/PDIF O
u
tput
D
SP HEA
D
E
R
C
S
5
341
O
sc.
AN
AL
OG
I
N
P
U
T
A
NAL
OG
OU
TPU
T
y
Si
ngl
e-Ende
d
Input
A
U
XILIAR
Y
AN
AL
OG
I
N
P
U
T
MC
LK D
ivided
C
lo
cks
/Da
ta
Ha
rd
wa
re
Se
tu
p
MCLK
B
U
S
Clocks & Data
C
locks/ Da
ta
Clocks/Data
I 2
C/
SP
I H
e
ade
r
Po
w
e
r
H
a
rd
w
a
re
Contr
o
l
Fi
gu
re
7
.
Blo
c
k
Di
a
g
ram
F
igure
8 on pa
ge
30
Fig
u
re 1
2
on pa
ge 34
to
F
igure 13
on
p
age 35
Figu
re 10 on
page
32
Figu
re 11 o
n
page
33
F
igure 9 on pa
ge 31
F
ig
u
re 2
0
on pag
e
42
F
igure 14
on
pa
ge 36 t
o
Fig
u
re 15 on pa
ge 37
Figure
2
5
o
n
page
47
F
igure 16
on
pa
ge 38 t
o
Figure
1
9
o
n
p
age
41
Figu
re 21 on pag
e 43 to
Figure
2
4
o
n
p
age
46
Figu
re 20 on pag
e 42