6 bypass control (address 06h), P 19 – Cirrus Logic CDB42438 User Manual
Page 19
CDB42438
DS646DB2
19
is held low for 300
µs whenever this bit changes.
5.5.3
RMCK/LRCK RATIO SELECT (128/256 FS)
Default = 0
0 - 256 Fs
1 - 128 Fs
Function:
Selects the RMCK/LRCK ratio for the CS8416. Pin 6 (RST bit) is held low for 300
µs whenever this
bit changes.
5.5.4
LEFT-JUSTIFIED OR I
²
S INTERFACE FORMAT (I
²
S/LJ)
Default = 0
0 - Left-Justified
1 - I
²
S
Function:
Selects either I
²
S or Left Justified interface format for the CS8416. Pin 6 (RST bit) is held low for 300
µs whenever this bit changes.
5.5.5
RMCK MASTERS MCLK BUS (RMCK_MASTER)
Default = 0
0 - Enabled
1 - Disabled
Function:
Enables/disables the external MCLK output buffer on the MCLK bus (see Figure 6 on page 13).
5.6
BYPASS CONTROL (ADDRESS 06H)
NOTE: To avoid contention with the FPGA, set the clock direction for the FPGA appropriately: FPGA->CODEC in
register 03h must be set to ‘1’b.
5.6.1
BYPASS FPGA (BYPASSFPGA)
Default = 1
0 - Enable
1 - Disable
Function:
This bit toggles a control line for the external data buffer to route the DSP directly to the CODEC.
7
6
5
4
3
2
1
0
BypassFPGA
DSPDATA
->DAC
Reserved
CS5341
->AUX
Reserved
Reserved
Reserved
Reserved