Cirrus Logic CDB42438 - Manual (Page 24)

CDB42438
24 DS646DB2
6. HARDWARE MODE
Switch S1 configures the CDB42438 in hardware mode. Switch S5 sets up the FPGA and con-
trols the routing of all clocks and data. Refer to section 6.1 for a list of the various hardware mode
options available. After setting any of these switches, the user may need to assert a reset by
pressing the “RESET” button (S4) or the “PROGRAM” button (S2) .
6.1 Setup Options
The setup options below allow the user to configure the CDB42438 when the CS42438 is in
hardware mode. The FPGA registers are programmed with the values shown in the table be-
low.
SW[3:0] General Description
Register
Address
Value Detail Description
0 0000 TDMer w/CS8416 Data (S/PDIF1)
1) CS8416 Masters MCLK & PCM Subclocks
2) CS8416 data duplicated and Time-Division
Multiplexed into DAC SDIN.
3) ADC1 (AIN1-2) de-multiplexed from
SDOUT1 and input into CS8406.
01h 00h TDM Conversion - CS8416 clocks & data to TDMer.
02h 03h SDIN Control - TDMer output data input to SDIN.
03h 36h CODEC Clock Control - CODEC slave to TDMer.
04h 61h CS8406 Control - ADC1 to CS8406.
05h 38h CS8416 Control - CS8416 masters MCLK bus and
provides PCM subclocks to the TDMer.
06h EFh Bypass Control - N/A.
07h 02h DSP Header - DSP Slave to MCLK.
08h 41h CS5341/Misc. Control - N/A.
1 0001 TDMer w/CS8416 Data (S/PDIF2)
1) CS8416 Masters MCLK & PCM Subclocks
2) CS8416 data duplicated and Time-Division
Multiplexed into DAC_SDIN.
3) ADC2 (AIN3-4) de-multiplexed from
ADC_SDOUT and input into CS8406.
01h 00h TDM Conversion - CS8416 clocks & data to TDMer.
02h 03h SDIN Control - TDMer output data input to SDIN.
03h 36h CODEC Clock Control - CODEC slave to TDMer.
04h 69h CS8406 Control - ADC2 to CS8406.
05h 38h CS8416 Control - CS8416 masters MCLK bus and
provides PCM subclocks to the TDMer.
06h EFh Bypass Control - N/A.
07h 02h DSP Header - DSP Slave to MCLK.
08h 41h CS5341/Misc. Control - N/A.
2 0010 TDMer w/CS8416 Data (S/PDIF3)
1) CS8416 Masters MCLK & PCM Subclocks
2) CS8416 data duplicated and Time-Division
Multiplexed into DAC_SDIN.
3) ADC3 (AIN5-6) de-multiplexed from
ADC_SDOUT and input into CS8406.
01h 00h TDM Conversion - CS8416 clocks & data to TDMer.
02h 03h SDIN Control - TDMer output data input to SDIN.
03h 36h CODEC Clock Control - CODEC slave to TDMer.
04h 71h CS8406 Control - ADC3 to CS8406.
05h 38h CS8416 Control - CS8416 masters MCLK bus and
provides PCM subclocks to the TDMer.
06h EFh Bypass Control - N/A.
07h 02h DSP Header - DSP Slave to MCLK.
08h 41h CS5341/Misc. Control - N/A.