Cirrus Logic CS42L55 - Manual (Page 36)

36 DS773F1
CS42L55
4.11.1 Recommended Power-Down Sequence
1. To minimize pops on the headphone or line amplifier, each respective analog volume control must
first be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]
2. Set the PDN bit to ‘1’b.
3. Bring RESET low.
4.12 Recommended PGA to HP or Line Power-Up Sequence (Analog Passthrough)
1. Hold RESET low until the power supplies are stable; no specific power supply sequencing is required.
RESET should be held low for a minimum of 1 ms after power supplies are stable.
2. Apply MCLK at the appropriate frequency.
3. Bring RESET high.
4. Wait a minimum of 500 ns before writing to the control port.
5. The default state of the master power down bit, PDN, is ‘1’b. Load the following register settings while
keeping the PDN bit set to ‘1’b.
6. Load the required register settings detailed in 4.13 “Required Initialization Settings” on page 37 .
7. Configure the headphone and line power down controls for ON, OFF, or HPDETECT operation.
Register Controls: PDN_HPx[1:0], PDN_LINx[1:0]
8. Configure the HP and/or Line amplifiers to receive the analog output from the PGA.
Register Controls: LINExMUX, HPxMUX
9. Power down the DSP engine.
Register Controls: PDN_DSP
10. To minimize pops on the headphone or line amplifier, each respective analog volume control must first
be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]
11. After muting the headphone and/or line amplifiers, set the PDN bit to ‘0’b.
12. Wait 75 ms for the headphone or line amplifier to power up.
13. Un-mute and ramp the volume for the headphone or line amplifiers to the desired level.
14. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to
prevent power glitch related issues.
4.12.1 Recommended Power-Down Sequence
1. To minimize pops on the headphone and/or line amplifier, each respective analog volume control
must first be muted and set to maximum attenuation.
Register Controls: HPxMUTE, LINExMUTE, HPxVOL[6:0], LINExVOL[6:0]
2. During power down, the CODEC attempts to power down on a zero cross transition of the analog
Power Down Sequence Register Location
Step 1 a ................................
Step 1 b ................................
Step 2 ..................................
“Headphone Volume Control” on page 57 , “Line Volume Control” on page 58
“Headphone Channel x Mute” on page 57 , “Line Channel x Mute” on page 58
“Power Down” on page 42
Power Up Sequence Register Location
Step 5 , 11 ............................
Step 7 ..................................
Steps 8 ................................
Step 9 ..................................
Step 10 a, 13 a .......................
Step 10 b, 13 b .......................
“Power Down” on page 42
“Power Control 2 (Address 03h)” on page 43
“ADC, Line, HP MUX (Address 08h)” on page 46
“Power Down DSP” on page 50
“Headphone Channel x Mute” on page 57
, “Line Channel x Mute” on page 58
“Headphone Volume Control” on page 57 , “Line Volume Control” on page 58