Cirrus Logic CS42L55 - Manual (Page 43)

DS773F1 43
CS42L55
6.3 Power Control 2 (Address 03h)
6.3.1 Headphone Power Control
Configures how the HPDETECT pin, 29, controls the power for the headphone amplifier.
6.3.2 Line Power Control
Configures how the HPDETECT pin, 29, controls the power for the line amplifier.
6.4 Clocking Control 1 (Address 04h)
6.4.1 Master/Slave Mode
Configures the serial port I/O clocking.
6.4.2 SCLK Polarity
Configures the polarity of the SCLK signal.
7 6 5 4 3 2 1 0
PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_LINB1 PDN_LINB0 PDN_LINA1 PDN_LINA0
PDN_HPx[1:0] Headphone Status
00
Headphone channel is ON when the HPDETECT pin, 29, is LO.
Headphone channel is OFF when the HPDETECT pin, 29, is HI.
01
Headphone channel is ON when the HPDETECT pin, 29, is HI.
Headphone channel is OFF when the HPDETECT pin, 29, is LO.
10 Headphone channel is always ON.
11 Headphone channel is always OFF.
PDN_LINx[1:0] Line Status
00
Line channel is ON when the HPDETECT pin, 29, is LO.
Line channel is OFF when the HPDETECT pin, 29, is HI.
01
Line channel is ON when the HPDETECT pin, 29, is HI.
Line channel is OFF when the HPDETECT pin, 29, is LO.
10 Line channel is always ON.
11 Line channel is always OFF.
7 6 5 4 3 2 1 0
Reserved Reserved M/S INV_SCLK SCK=MCK1 SCK=MCK0 MCLKDIV2 MCLKDIS
M/S Serial Port Clocks
0 Slave (Input ONLY)
1 Master (Output ONLY)
Application: “Serial Port Clocking” on page 34
INV_SCLK SCLK Polarity
0 Not Inverted
1 Inverted