Cirrus Logic CDB42L56 - Manual (Page 10)

10 DS851DB1
CDB42L56
3.2 PSIA In to Analog Out and Analog In to PSIA Out
The CS42L56 ADC and DAC performance can be tested by loading the “PSIA In to Analog Out -- Analog
In to PSIA Out” quick setup file provided with the software package. The script configures the digital clock
and data signal routing on the board as shown in
Figure 2 . The quick setup scripts provided in the software
assume that a 24.000 MHz on-board oscillator is populated in Y1.
Line Output
B
A
HP Output J21
32
32
16
16
J4
J12
B
A
AIN1A
AIN1B
AIN2A
AIN2B
AIN3A
AIN3B
J19
J20
LRCK
CS42L56
SCLK
SDIN
(SLAVE)
MCLK
SDOUT
LINEOUTB
LINEOUTA
HPOUTB
HPOUTA
AIN1A
AIN1B
AIN2A
AIN2B
AIN3A
AIN3B
FPGA
PLL
Divider
Divider Divider
On-Board
Oscillator
Tx SRC
(CS8421)
(SLAVE)
ISCLK
ILRCK
SDIN
OSCLK
OLRCK
SDOUT
XTI
PSIA Tx (J78)
TX.SCLK
TX.LRCK
TX.SDOUT
PSIA Rx (J40)
RX.SCLK
RX.LRCK
RX.SDIN
TX.MCLK
RX.MCLK
Rx SRC
(CS8421)
(SLAVE)
ISCLK
ILRCK
SDIN
OSCLK
OLRCK
SDOUT
XTI
(MASTER)
(MASTER)
Figure 3. PSIA In to Analog Out and Analog In to PSIA Out