Cirrus Logic CDB42L56 - Manual (Page 6)

6 DS851DB1
CDB42L56
1.6 Oscillator
The socketed on-board oscillator (Y1) can be selected as the system master clock source by using the se-
lections on the “Board Configuration” tab of the Cirrus FlexGUI.
Section 4 on page 11 provides software
configuration details.
The oscillator is mounted in pin sockets, allowing easy removal or replacement. The device footprint on the
board will accommodate half-can or full-can sized oscillators.
1.7 PLL
An on-board PLL is used with the FPGA to generate the serial port sub-clocks for the CS42L56’s serial port
when the CS42L56 is set to slave mode. The sub-clocks’ frequencies are selected on the “Board Configu-
ration” tab of the Cirrus FlexGUI.
Section 4 on page 11 provides software configuration details.
1.8 I/O Stake Headers
Headers J104 and J109 ( Figure 35 on page 28 ) provide unbuffered bidirectional access to the CS42L56
serial port and control port, respectively. For regular operation, the left two pins on all rows should be shunt-
ed to allow the CS42L56 to receive serial and control port data and clocks from the on-board FPGA.
Alternatively, the stake headers provide access to the CS42L56 from external systems simply by removing
all the shunt jumpers from the “USB” and “CDB I/O” positions. The user may then connect a ribbon cable
connector to the “Ext. Sys. Connect” pins for external control of board functions. A single row of “GND” pins
is provided to maintain signal ground integrity. Two unpopulated pull-up resistors are also available should
the user choose to use the CDB42L56 logic supply (VL) externally.
If an external system is used to interface with the CS42L56 through headers J104 and J109, the digital I/O
logic voltage levels must be selected cautiously since the lines between the headers and the device are not
buffered. Please refer to the CS42L56 product data sheet for a detailed explanation on digital I/O interface
specifications. Selections are made using the “Board Configuration” tab of the Cirrus FlexGUI software.
Section 4 on page 11 provides software configuration details.
1.9 CS42L56 Audio Codec
A complete description of the CS42L56 (U3 - Figure 35 on page 28 ) can be found in the CS42L56 product
data sheet.
The CS42L56 is configured using the Cirrus Logic Windows compatible software FlexGUI. The device con-
figuration registers are directly accessible via the “Register Maps” tab of the Cirrus FlexGUI software. This
tab provides low-level control of each bit. For easier configuration, additional tabs provide high-level control.
Section 4 on page 11 provides software configuration details.
1.10 Analog Inputs
The analog input circuitry on the CDB42L56 has been designed to allow for testing of the CS42L56 in all its
possible analog input configurations. Line or microphone level analog input signals can be provided to the
analog inputs on the CS42L56 through RCA or microphone input jacks (
Figure 35 on page 28 ). Stake head-
er J6 allows the user to select (with jumpers installed) the CS42L56 as the microphone bias source for each
microphone input (CAUTION: Only 2 jumpers may be installed at a time).
Headers J19 and J20 are used to select the desired input for pins AIN3A/AIN1REF and AIN3B/AIN2REF
on the CS42L56. These headers can be used to select between either a single-ended or a pseudo-differ-
ential analog input setup.
Table 1 provides jumper and resistor settings for the various analog input config-
urations allowed on the CS42L56. The shaded rows in the table indicate the most commonly used
configurations and do not require any extra resistor modifications.