Cirrus Logic CDB42L56 - Manual (Page 3)

DS851DB1 3
CDB42L56
Figure 17. Fade-to-Noise Linearity - Analog In to Digital Out ................................................................... 22
Figure 18. THD+N vs. Freq. - Digital In to HP Out .................................................................................... 22
Figure 19. THD+N vs. Amplitude - Digital In to HP Out ............................................................................ 22
Figure 20. THD+N vs. Volume - Digital In to HP Out ................................................................................ 23
Figure 21. FFT - Digital In to HP Out @ 0 dBFS ....................................................................................... 23
Figure 20. FFT - Digital In to HP Out @ -60 dBFS .................................................................................... 23
Figure 21. FFT - Digital In to HP Out - No Input ........................................................................................ 23
Figure 22. FFT - Digital In to HP Out - No Input Wideband ...................................................................... 23
Figure 23. FFT Crosstalk - Digital In to HP Out @ 0 dBFS ....................................................................... 23
Figure 24. Freq. Response - Digital In to HP Out ..................................................................................... 24
Figure 25. Fade-to-Noise Linearity- Digital In to HP Out ........................................................................... 24
Figure 26. THD+N vs. Freq. - Digital In to Line Out .................................................................................. 24
Figure 27. THD+N vs. Amplitude - Digital In to Line Out .......................................................................... 24
Figure 28. THD+N vs. Volume - Digital In to Line Out .............................................................................. 25
Figure 29. FFT Crosstalk - Digital In to Line Out @ 0 dBFS ..................................................................... 25
Figure 28. FFT - Digital In to Line Out @ 0 dBFS ..................................................................................... 25
Figure 29. FFT - Digital In to Line Out @ -60 dBFS .................................................................................. 25
Figure 30. FFT - Digital In to Line Out - No Input ...................................................................................... 25
Figure 31. FFT - Digital In to Line Out - No Input Wideband ..................................................................... 25
Figure 32. Freq. Response - Digital In to Line Out .................................................................................... 26
Figure 33. Fade-to-Noise Linearity- Digital In to Line Out ......................................................................... 26
Figure 34. Block Diagram .......................................................................................................................... 27
Figure 35. CS42L56 & Analog I/O (Schematic Sheet 1) ........................................................................... 28
Figure 36. S/PDIF & Digital Interface (Schematic Sheet 2) ...................................................................... 29
Figure 37. PLL, oscillator and external I/O connections (Schematic Sheet 3) .......................................... 30
Figure 38. Microcontroller and FPGA (Schematic Sheet 4) ...................................................................... 31
Figure 39. Power (Schematic Sheet 5) ..................................................................................................... 32
Figure 40. Silk Screen ............................................................................................................................... 33
Figure 41. Top-Side Layer ........................................................................................................................ 34
Figure 42. GND (Layer 2) .......................................................................................................................... 35
Figure 43. Power (Layer 3) ....................................................................................................................... 36
Figure 44. Bottom Side Layer ................................................................................................................... 37
LIST OF TABLES
Table 1. Analog Input Configuration Jumper and Resistor Settings ........................................................... 7
Table 2. System Connections ................................................................................................................... 18
Table 3. Jumper Settings .......................................................................................................................... 19