Cirrus Logic CS5460A - Manual (Page 30)

CS5460A
30 DS487F5
pins of the voltage/current channels to their ground
reference level. (See Figure 17.)
Offset and gain calibration cannot be done at the
same time. This will cause undesirable calibration
results.
3.8.7 Description of Calibration Algo-
rithms
The computational flow of the CS5460A’s AC and
DC gain/offset calibration sequences are illustrat-
ed in Figure 18. This figure applies to both the volt-
age channel and the current channel. The
following descriptions of calibration sequences will
focus on the voltage channel, but apply equally to
the current channel.
Note: For proper calibration, it is assumed that the value
of the Voltage-/Current-Channel Gain Registers
are set to default (1.0) before running the gain
calibration(s), and the value in the
Voltage-/Current Channel AC and DC Offset
Registers is set to default (0) before running
calibrations. This can be accomplished by a
software or hardware reset of the device. The
values in the voltage/current calibration registers
do affect the results of the calibration sequences.
3.8.7.1 AC Offset Calibration Sequence
The idea of the AC offset calibration is to obtain an
offset value that reflects the square of the RMS
output level when the inputs are grounded. During
normal operation, when the CS5460A is calculat-
ing the latest result for the RMS Voltage Register,
this AC offset register value will be subtracted from
the square of each successive voltage sample in
order to nullify the AC offset that may be inherent
in the voltage-channel signal path. Note that the
value in the AC offset register is proportional to the
square of the AC offset.
First, the inputs are grounded, and then the AC off-
set calibration command is sent to the CS5460A.
When the AC offset calibration sequence is initiat-
ed, a valid RMS Voltage Register value is acquired
and squared. This value is then subtracted from
the square of each voltage sample that comes
through the RMS data path. See Figure 18.
+
-
XGAIN
+
-
External
Connections
+
-
AIN+
AIN-
CM +-
Full Scale
(DC or AC)
Figure 16. System Calibration of Gain.
+
-
XGAIN
+
-
External
Connections
0V +
-
AIN+
AIN-
CM + -
Figure 17. System Calibration of Offset.
In Modulator + x
to V*, I*, P*, E* Registers
Filter
N
V RMS
N 

SINC
DC Offset* Gain*
+ X
2
-X
1
x
N
AC Offset*
X
2
0.6
x
+ +
- +
2 * 
* Denotes readable/writable register
X N
Figure 18. Calibration Data Flow