Switching characteristics, Cs5460a – Cirrus Logic CS5460A User Manual
Page 9
CS5460A
DS487F5
9
SWITCHING CHARACTERISTICS
(T
A
= -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels:
Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF))
Notes: 24. Device parameters are specified with a 4.096 MHz clock, yet, clocks between 3 MHz to 20 MHz can be
used. However, for input frequencies over 5 MHz, an external oscillator must be used.
25. If external MCLK is used, then duty cycle must be between 45% and 55% to maintain this specification.
26. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
Parameter
Symbol Min Typ
Max
Unit
Master Clock FrequencyCrystal/Internal Gate Oscillator (Note 24)
MCLK
2.5
4.096
20
MHz
Master Clock Duty Cycle
40
-
60
%
CPUCLK Duty Cycle
40
60
%
Rise Times
Any Digital Input Except SCLK (Note 26)
SCLK
Any Digital Output
t
rise
-
-
-
-
-
50
1.0
100
-
µs
µs
ns
Fall Times
Any Digital Input Except SCLK (Note 26)
SCLK
Any Digital Output
t
fall
-
-
-
-
-
50
1.0
100
-
µs
µs
ns
Start-up
Oscillator Start-Up Time
XTAL = 4.096 MHz (Note 27)
t
ost
-
60
-
ms
Serial Port Timing
Serial Clock Frequency
SCLK
-
-
2
MHz
Serial Clock
Pulse Width High
Pulse Width Low
t
1
t
2
200
200
-
-
-
-
ns
ns
SDI Timing
CS Falling to SCLK Rising
t
3
50
-
-
ns
Data Set-up Time Prior to SCLK Rising
t
4
50
-
-
ns
Data Hold Time After SCLK Rising
t
5
100
-
-
ns
SCLK Falling Prior to CS Disable
t
6
100
-
-
ns
SDO Timing
CS Falling to SDI Driving
t
7
-
20
50
ns
SCLK Falling to New Data Bit
t
8
-
20
50
ns
CS Rising to SDO Hi-Z
t
9
-
20
50
ns
Auto-boot Timing
Serial Clock
Pulse Width High
Pulse Width Low
t
10
t
11
8
8
MCLK
MCLK
MODE setup time to RESET Rising
t
12
50
ns
RESET rising to CS falling
t
13
48
MCLK
CS falling to SCLK rising
t
14
100
8
MCLK
SCLK falling to CS rising
t
15
16
MCLK
CS rising to driving MODE low (to end auto-boot sequence).
t
16
50
ns
SDO guaranteed setup time to SCLK rising
t
17
100
ns