Register descriptions, 1 configuration register, Figure 21. cs5460a register diagram – Cirrus Logic CS5460A User Manual
Page 44: Nd figure 21, Section 5), Cs5460a
CS5460A
44
DS487F5
5. REGISTER DESCRIPTIONS
Note: 1. ** “default” => bit status after software or hardware reset
2. Note that all registers can be read from, and written to.
5.1 Configuration Register
Address: 0
Default** = 0x000001
K[3:0]
Clock divider. A 4 bit binary number used to divide the value of MCLK to generate the internal
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero).
iCPU
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = normal operation (default)
1 = minimize noise when CPUCLK is driving rising edge logic
IHPF
Control the use of the High Pass Filter on the Current Channel.
0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used.
(default)
1 = High-pass filter is enabled.
VHPF
Control the use of the High Pass Filter on the voltage Channel.
0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used.
(default)
1 = High-pass filter enabled
23
22
21
20
19
18
17
16
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Gi
15
14
13
12
11
10
9
8
EWA
Res
Res
SI1
SI0
EOD
DL1
DL0
7
6
5
4
3
2
1
0
RS
VHPF
IHPF
iCPU
K3
K2
K1
K0
Current
Channel
Voltage
Channel
Cycle-Counter Registe
Status Register (1 × 24)
Serial Interface
Mask Register (1 × 24)
Unsigned Output Registers (2 × 24)
(I
, V
)
Command Word
State Machine
Transmit Buffer
Receive Buffer
Signed Output Registers (4 × 24)
(I, V, P, E)
RMS
RMS
24-Bit
SDI
CS
SDO
SCLK
INT
AC Offset Register (1 x 24)
AC Offset Register (1 x 24)
Control Register (1 x 24)
Power Offset Register (1 x 24)
Configuration Register (1 × 24)
Pulse-Rat e Register (1 × 24)
Offset Register (1 × 24)
DC
Offset Register (1 × 24)
DC
Gain Register (1 × 24)
AC/DC
Gain Register (1 × 24)
AC/DC
r (1 × 24)
Timebase Cal. Register (1 x 24)
Figure 21. CS5460A Register Diagram