Cirrus Logic CS5484 - Manual (Page 24)

CS5484
24 DS981F3
5.5.1 Pulse Rate
Before configuring the PulseRate register, the full-scale
pulse rate needs to be calculated and the frequency
range needs to be specified through FREQ_RNG[3:0]
bits in the PulseWidth register. Refer to section
6.6.6
Pulse Output Width (PulseWidth) – Page 0, Address 8
on page 41. The FREQ_RNG[3:0] bits should be set to
b[0110]. For example, if a meter has the meter constant
of 1000imp/kWh, a maximum voltage (U
MAX
) of 240 V,
and a maximum current (I
MAX
) of 100A, the maximum
pulse rate is:
[1000x(240x100/1000)]/3600 = 6.6667Hz.
Assume the meter is calibrated with U
MAX
and I
MAX
,
and the Scale register contains the default value of 0.6.
After gain calibration, the power register value will be
0.36, which represents 240x100 = 24kW or 6.6667Hz
pulse output rate. The full-scale pulse rate is:
F
out
= 6.6667/0.36 = 18.5185Hz.
The CS5484 pulse generation block behaves as
follows:
• The pulse rate generated by full-scale (1.0decimal)
power register is:
F
OUT
= (PulseRatex2000)/2 FREQ_RNG
• The PulseRate register value is:
PulseRate = (F
OUT
x2 FREQ_RNG )/2000
= (18.5186x64)/2000
= 0.5925952
= 0x4BDA29
5.5.2 Pulse Width
The PulseWidth register defines the Active-low time of
each energy pulse:
Active-low = 250µs+(PulseWidth/64000).
By default, the PulseWidth register value is 1, and the
Active-low time of each energy pulse is 265.6µs. Note
that the pulse width should never exceed the pulse
period.
5.6 Voltage Sag, Voltage Swell, and
Overcurrent Detection
Voltage sag detection is used to determine when the
voltage falls below a predetermined level for a specified
interval of time (duration). Voltage swell and overcurrent
detection determine when the voltage or current rises
above a predetermined level for the duration.
The duration is set by the value in the V1Sag
DUR
(V2Sag
DUR
), V1Swell
DUR
(V2Swell
DUR
), and
I1Over
DUR
(I2Over
DUR
) registers. Setting any of these
to zero (default) disables the detect feature for the given
channel. The value is in output word rate (OWR)
samples. The predetermined level is set by the values
in the V1Sag
LEVEL
(V2Sag
LEVEL
), V1Swell
DUR
(V2Swell
DUR
), and I1Over
LEVEL
(I2Over
LEVEL
) registers.
For each enabled input channel, the measured value is
rectified and compared to the associated level register.
Over the duration window, the number of samples
above and below the level are counted. If the number of
samples below the level exceeds the number of
samples above, a Status0 register bit V1SAG (V2SAG)
is set, indicating a sag condition. If the number of
samples above the level exceeds the number of
samples below, a Status0 register bit V1SWELL
(V2SWELL) or I1OVER (I2OVER) is set, indicating a
swell or overcurrent condition (see
Figure 15 ).
L e v e l
D u ra tio n
Figure 15. Sag, Swell, and Overcurrent Detect