2 hardware registers, Cs5484 – Cirrus Logic CS5484 User Manual
Page 29
CS5484
DS981F3
29
6.2 Hardware Registers Summary (Page 0)
Address
2
RA[5:0]
Name
Description
1
DSP
3
HOST
3
Default
0*
00 0000
Config0
Configuration 0
Y
Y
0x 40 0000
1*
00 0001
Config1
Configuration 1
Y
Y
0x 00 EEEE
2
00 0010
Reserved
-
3*
00 0011
Mask
Interrupt Mask
Y
Y
0x 00 0000
4
00 0100
-
Reserved
-
5*
00 0101
PC
Phase Compensation Control
Y
Y
0x 00 0000
6
00 0110
-
Reserved
-
7*
00 0111
SerialCtrl
UART Control
Y
Y
0x 02 004D
8*
00 1000
PulseWidth
Energy Pulse Width
Y
Y
0x 00 0001
9*
00 1001
PulseCtrl
Energy Pulse Control
Y
Y
0x 00 0000
10
00 1010
-
Reserved
-
11
00 1011
-
Reserved
-
12
00 1100
-
Reserved
-
13
00 1101
-
Reserved
-
14
00 1110
-
Reserved
-
15
00 1111
-
Reserved
-
16
01 0000
-
Reserved
-
17
01 0001
-
Reserved
-
18
01 0010
-
Reserved
-
19
01 0011
-
Reserved
-
20
01 0100
-
Reserved
-
21
01 0101
-
Reserved
-
22
01 0110
-
Reserved
-
23
01 0111
Status0
Interrupt Status
N
N
0x 80 0000
24
01 1000
Status1
Chip Status 1
N
N
0x 80 1800
25
01 1001
Status2
Chip Status 2
N
N
0x 00 0000
26
01 1010
-
Reserved
-
27
01 1011
-
Reserved
-
28
01 1100
-
Reserved
-
29
01 1101
-
Reserved
-
30
01 1110
-
Reserved
-
31
01 1111
-
Reserved
-
32
10 0000
-
Reserved
-
33
10 0001
-
Reserved
-
34*
10 0010
RegLock
Register Lock Control
N
N
0x 00 0000
35
10 0011
-
Reserved
-
36
10 0100
V1
PEAK
V1 Peak Voltage
N
Y
0x 00 0000
37
10 0101
I1
PEAK
I1 Peak Current
N
Y
0x 00 0000
38
10 0110
V2
PEAK
V2 Peak Voltage
N
Y
0x 00 0000
39
10 0111
I2
PEAK
I2 Peak Current
N
Y
0x 00 0000
40
10 1000
-
Reserved
-
41
10 1001
-
Reserved
-
42
10 1010
-
Reserved
-
43
10 1011
-
Reserved
-
44
10 1100
-
Reserved
-
45
10 1101
-
Reserved
-
46
10 1110
-
Reserved
-
47
10 1111
-
Reserved
-
48
11 0000
PSDC
Phase Sequence Detection & Control N
Y
0x 00 0000
49
11 0001
-
Reserved
-
50
11 0010
-
Reserved
-
51
11 0011
-
Reserved
-
52
11 0100
-
Reserved
-