Document Outline

• CS61584A
  • Features
  • Description
  • TABLE OF CONTENTS
  • LIST OF TABLES
  • LIST OF FIGURES
  • 1. CHARACTERISTICS AND SPECIFICATIONS
    • ABSOLUTE MAXIMUM RATINGS
    • RECOMMENDED OPERATING CONDITIONS
    • ANALOG CHARACTERISTICS
    • DIGITAL CHARACTERISTICS
    • SWITCHING CHARACTERISTICS
      • Figure 1. Signal Rise And Fall Characteristics
      • Figure 2. Recovered Clock and Data Switching Characteristics
      • Figure 3. Transmit Clock and Data Switching Characteristics
    • SWITCHING CHARACTERISTICS - SERIAL PORT
      • Figure 4. Serial Port Write Timing Diagram
      • Figure 5. Serial Port Read Timing Diagram
    • SWITCHING CHARACTERISTICS - PARALLEL PORT
      • Figure 6. Parallel Port Timing - Motorola Mode
      • Figure 7. Parallel Port Timing - Intel Read Mode
      • Figure 8. Parallel Port Timing - Intel Write Mode
      • Figure 9. Parallel Port Timing - Motorola Mode to RAM
      • Figure 10. Parallel Port Timing - Intel Read Mode from RAM or ROM
      • Figure 11. Parallel Port Timing - Intel Write Mode to RAM
    • SWITCHING CHARACTERISTICS - JTAG
      • Figure 12. JTAG Switching Characteristics
  • 2. OVERVIEW
    • Figure 13. Examples of CS61584A Applications
    • 2.1 AT&T 62411 Customer Premises Application
    • 2.2 Asynchronous Multiplexer Application
    • 2.3 Synchronous Application
  • 3. TRANSMITTER
    • Figure 14. Typical Pulse Shape at DSX-1 Cross Connect
    • Figure 15. Mask of the Pulse at the 2048 kbps Interface
    • Table 1. Line Configuration Selections
  • 4. RECEIVER
    • Figure 16. Minimum Input Jitter Tolerance of Receiver (Clock Recovery Circuit and jitter Attenuator)
    • Table 2. Recovered Data/Clock Options
    • Figure 17. Typical Jitter Transfer Function
  • 5. JITTER ATTENUATOR
    • Table 3. Jitter Attenuation Control
  • 6. REFERENCE CLOCK
  • 7. POWER-UP RESET
  • 8. LINE CONTROL AND MONITORING
    • 8.1 Line Code Encoder/Decoder
    • 8.2 Alarm Indication Signal
    • 8.3 Bipolar Violation Detection
    • 8.4 Excessive Zeros Detection
    • 8.5 Loss of Signal
    • 8.6 Transmit All Ones
    • 8.7 Receive All Ones
    • 8.8 Local Loopback
    • 8.9 Remote Loopback
    • 8.10 Driver Tristate
    • 8.11 Power Down
    • 8.12 Reset Pin
  • 9. HOST MODE
    • 9.1 Register Set
      • Table 4. CS61584A Register Set
      • 9.1.1 Status Registers
        • Table 5. Status Registers
        • Figure 18. Alarm Indication Event Relationships
      • 9.1.2 Mask Registers
        • Table 6. Mask Registers
      • 9.1.3 Control A Registers
        • Table 7. Control A Registers
      • 9.1.4 Control B Registers
        • Table 8. Control B Registers
      • 9.1.5 Arbitrary Waveform Registers
        • Table 9. Arbitrary Waveform Registers
        • Figure 19. Phase Definition of Arbitrary Waveforms
        • Figure 20. Example of Summing of Waveforms
    • 9.2 Serial Port Operation
      • Figure 21. Serial Read/Write Format (SPOL = 0)
      • Figure 22. Address Command byte
    • 9.3 Parallel Port Operation
  • 10. JTAG BOUNDARY SCAN
    • Figure 23. JTAG Circuitry Block Diagram
    • 10.1 JTAG Data Registers (DR)
      • Table 10. Boundary Scan Register
      • Table 11. Device Identification Register
    • 10.2 JTAG Instructions and Instruction Register (IR)
      • Tabl e 1 2.
    • 10.3 JTAG TAP Controller
      • Figure 24. TAP Controller State Diagram
    • 10.4 Test-Logic-Reset State
    • 10.5 Run-Test/Idle State
    • 10.6 Select-DR-Scan State
    • 10.7 Capture-DR State
    • 10.8 Shift-DR State
    • 10.9 Exit1-DR State
    • 10.10 Pause-DR State
    • 10.11 Exit2-DR State
    • 10.12 Update-DR State
    • 10.13 Select-IR-Scan State
    • 10.14 Capture-IR State
    • 10.15 Shift-IR State
    • 10.16 Exit1-IR State
    • 10.17 Pause-IR State
    • 10.18 Exit2-IR State
    • 10.19 Update-IR State
    • 10.20 JTAG Application Examples
      • Figure 25. JTAG Instruction Register update
      • Figure 26. JTAG Data Register update
  • 11. PIN DESCRIPTIONS
  • 12. PACKAGE DIMENSIONS
  • 13. APPLICATIONS
    • Figure 27. Hardware Mode Configuration
    • Table 13. CS61584A External Components
    • 13.1 Line Interface
      • Figure 28. Host Mode Serial Port Configuration
      • Figure 29. Host Mode Parallel Port Configuration
    • 13.2 Power Supply
    • 13.3 Quartz Crystal Specifications
      • Table 14. Quartz Crystal Specifications
      • Table 15. Suggested Quartz Crystals
    • 13.4 Crystal Oscillator Specifications
      • Table 16. Suggested Crystal Oscillators
    • 13.5 Transformers
      • Table 17. Transformer Specifications
      • Table 18. Recommended Transformers
    • 13.6 Designing for AT&T 62411
    • 13.7 Line Protection
    • 13.8 Loop Selection Equations
• Ordering Information