Vicor PI33XX-2X I2C Digital Interface Guide - Manual (Page 12)

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PI33XX-2X I
2
C Digital Interface Guide
Figure 11 - I
2
C Bus Capture
Configuration Programming
The PI33XX-2X has three programming registers that can be changed by the user as a one time change only. Of
each register, any bit that is not set may be set. The programming requires burning internal fuse links as
permanent memory. Once they are burned there is no way to change or reset the settings back to default. For this
reason, it is critical to be sure the settings are correct prior to clicking on the burn button. The three registers are
ENA_POL, SYN[3:0] and KBIT2. ENA_POL is programmed by using the “ENA POL” soft key and dialog box. SYN[3:0]
is programmed by the “SYNC” soft key and dialog box. KBIT2 is programmed using the “KILL BIT2” soft key and
dialog box.
The programmable values for the SYN[3:0] register are shown in Table 5. Bits 0 through 2 define the delay setting
between a synchronizing signal (rising or falling edge as selected) applied to the SYNCI input and the SYNCO output
rising edge, applied as a fraction of the main system clock period (MP). The most significant bit SYN[3] determines
which edge trigger occurs. A “1” indicates rising edge and a “0” indicates falling edge. As an example, if the MP
value is 1 us, and the SYNC dialog box reads “1101”, the programmed delay is 500 ns from the rising edge of the
SYNCI input. The actual programmed value does not take effect until the bits are actually burned so there is no way
to measure the delay without actually burning the value in. For this reason, the user should review the waveform
plots in Figures 12 through 19 to understand the timing relationship prior to attempting to burn the values into the
register. The value of main system clock can be found in the PI33XX-2X datasheet for each part number.
To understand the relationship between the synchronization timing and the PI33XX-2X operation, an overview of
the PI33XX-2X power train timing is shown in Figure 12. There are three main timing states in the ZVS Buck
Topology; T1, T3 and T4 as defined below:
T1: T1 defines the start of a power cycle when the clamp switch has opened and the zero voltage switching
resonant action has started, followed by the turn on of Q1 and continuing until Q1 turns off. During T1, current
ramps up to a positive peak value, charge is delivered to the output capacitor and energy is stored in the output
inductor.
T3: Q1 has turned off, Q2 has turned on and energy stored in the inductor is delivered to the load. As the current
in the inductor passes through zero, energy is stored in the inductor to provide zero voltage switching for the next
time Q1 is required to turn on.