Rockwell Automation SB3000 AC Power Modules - Manual (Page 75)

SB3000 Interlock Sequencing D-1
A
PPENDIX
D
SB3000 Interlock Sequencing
When a request is made to turn on the SB3000 Power Module’s voltage loop and a
required precondition has not been met, a bit will be set in Interlock register 205/1205
indicating the problem. The interlock requirements are described in the following table.
If an interlock problem is detected, the voltage loop will not go into run.
Interlock Precondition
Bit Set in Register
205/1205 by the PMI
Processor
Valid configuration parameters have not been downloaded into the UDC
module from the Programming Executive or the parameters are outside of
acceptable limits. Bit 0 (IC_CNF@)
Pre-defined local tunables are zero or a UDC task containing the variables has
not been loaded to the rack. Bit 1 (IC_GAIN@)
The RPI input is not turned on. Bit 2 (IC_RPI@)
A fault that shut down the voltage loop has not been reset. Bit 3 (IC_FLT@)
A rising edge is not detected on a command bit in register 100/1100. Bit 4 (IC_RISE@)
More than one operating mode is requested at a time. Bit 5 (IC_MORE@)
The pre-charge contactor has not closed. Bit 7 (IC_PCHG@)
The number of GDI modules in the PMI rack does not match the number of GDI
modules configured or the GDI modules have been incorrectly placed in the
PMI rack. Bit 8 (IC_GDI@)
During the bridge test, a Power Module has not been selected or an incorrect
Power Module been selected. Bit 8 (IC_GDI@)
The PMI rack has an incorrect backplane. Bit 9 (IC_IPBP@)
The bridge test is requested and the DC bus voltage is greater than 10V. Bit 11 (IC_VDC@)