Spi interrupt enable register [0xc0cc] [r/w, Spi status register [0xc0ce] [r – Cypress EZ-OTG CY7C67200 User Manual

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Spi interrupt enable register [0xc0cc] [r/w, Spi status register [0xc0ce] [r | Cypress EZ-OTG CY7C67200 User Manual | Page 56 / 78 Spi interrupt enable register [0xc0cc] [r/w, Spi status register [0xc0ce] [r | Cypress EZ-OTG CY7C67200 User Manual | Page 56 / 78
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