Hss receive address register [0xc078] [r/w, Hss receive counter register [0xc07a] [r/w – Cypress EZ-OTG CY7C67200 User Manual
Page 47
CY7C67200
Document #: 38-08014 Rev. *G
Page 47 of 78
HSS Receive Address Register
[0xC078] [R/W]
Figure 52. HSS Receive Address Register
Register Description
The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block receive transfer.
HSS Receive Counter Register
[0xC07A] [R/W]
Figure 53. HSS Receive Counter Register
Register Description
The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. This register must be
loaded with the word count minus one to start the block receive transfer. As each byte is received this register value is decre-
mented. When read, this register indicates the remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When
the transfer is complete this register returns 0x03FF until reloaded.
Reserved
All reserved bits must be written as ‘0’.
Bit #
15
14
13
12
11
10
9
8
Field
Address...
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Address
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Counter...
Read/Write
-
-
-
-
-
-
R/W
R/W
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Counter
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0