Maxim Integrated 71M6534 Energy Meter IC Family Software - Manual (Page 99)

71M653X Software User’s Guide
5.17 PORTING 71M6511/6513 CODE TO THE 71M653X
5.17.1 Flash Use
The biggest issue when moving code from the 6511/6513 to the 71M653x is the increased program memory. While the
71M6511 and 6513 have 64K, the 71M6531 has 128K and the 71M6534 has 256K. The 653x defaults to a 64K
configuration, so code from earlier meter chips will fit easily.
Creating banked code that uses the extra flash is a substantial discussion in itself. See the section “Creating banked
code.”
5.17.2 Extra RAM
The MPU now has access to 4K of RAM, up from 2K. Roughly 1K is allocated to the CE, leaving 3K.
5.17.3 CE Data Location is at XDATA 0x0000
CE data now resides in roughly the first 1K bytes of RAM, from 0x0000 to 0x03FF. The exact CE RAM usage varies
with different CE code versions, with single-phased CE codes taking less RAM, and three-phase CE codes taking up to
the limit. Nonstandard CE codes may take more than 1K, but these will come with instructions.
Standard CE configuration begins at 0x0010. Standard CE output areas begin at 0x0200.
The Keil compiler must be configured to avoid the CE RAM. If not, both the CE code and MPU code will misbehave
when the MPU writes data into the CE code’s internal data area and vice-versa.
5.17.4 CE Data Access is Transparent to the MPU
The MPU can now simply read and write the CE RAM. No special buffering or access routines are required.
The demo code, for example, no longer copies data from the CE’s output area to the MPU RAM. The Keil C code
simply uses the CE’s output data.
It’s fast to access the CE’s output as PDATA variables, so in the demo code, the PDATA page register (SFR 0xB7) is
set to 0x200. The CE output registers begin on a page boundary, 0x200.
5.17.5 Read-only areas in MPU RAM
The direct-memory-access ADC writes automatically to XDATA locations 0x0000..0x000E, so these are not stable for
memory tests, and there is no way to disable the writes. Also 0x000F is a read-only alternate location of the chip’s
version identification.
5.17.6 CE Code Location
Another difference between 71M6511/6513 and the 71M653x is that the CE code now resides in the flash. It is not
copied to the CE program RAM as in the 71M651X chips. Instead, the register CE_LCTN, bits 0…7 at XDATA 0x20A8
is set to the most significant 8 bits of the program flash address where the CE program resides. It is best to place the
CE program in a high code bank so it does not compete with the MPU for flash. The demo code puts it near the end of
the last bank.
5.17.7 CE Causes Flash Write-Protection
Since the CE resides in flash memory, there are safeguards that prevent the CE program memory from being erased or
reprogrammed while the CE is running.
When programming flash memory from an emulator, the CE must first be disabled by writing 00 to XDATA 0x2000.
Only then, programming of the flash memory can occur.
Most practical flash write code simply disables the CE, writes the flash, and enables the CE. This is the fastest way to
write the flash, and the metering values for the disabled period can be interpolated.
Automated flash writes with the CE running are theoretically possible. The writes have to be synchronized with an
interrupt from the correct (trailing) edge of the CE_BUSY signal. Also, with three phase CE code, there is usually only
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