Maxim Integrated 78M6631 - Manual (Page 16)

78M6631 Firmware Description Document UG_6631_078
16 Rev 2
To calibrate the voltage and current the following steps are required:
•
AC Source and Load: The calibration routine needs a stable source and load. The source and load
can be applied to a single phase, two phases or all three phases.
• Selection of Target Values: Before launching the calibration the target value (voltage/current) must
be set. During calibration the gains will be adjusted to match the target voltage and/or current.
• Selection of the Gain to Calibrate and Launch: the gain calibration can be performed on one
phase or multiple phases and can be voltage, current or both simultaneously. The control register
allows the selection of the channel to calibrate and the launch of the calibration routine.
Upon a successful calibration the command register will have the bits set for calibration reset to 0.
Upon unsuccessful calibration the command register will have the bits set for all failing channels.
2.3.6 Phase Error Compensation
The 78M6631 is designed to function with a variety of current transducers, including those that induce
inherent phase errors. A phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT).
These phase errors can vary from part to part, and they must be corrected to achieve accurate power
readings. The errors associated with phase mismatch are particularly noticeable at low power factors. The
78M6631 provides a means of digitally calibrating these small phase errors by introducing a time delay or
a time advance.
A Phase Compensation register is provided for each of the 3 phases. The range for phase
compensation is ±20° at 50 Hz. Phase compensation registers are set to 0.0 by default. Positive
values increase delay on voltages relative to currents. The default is ideal when using resistive
shunts for current measurement. But a compensation value will be required to compensate for the
induced delay of a current transformer or external filter.
Phase compensation registers use a signed (two’s complement) fixed-point notation. Bits 15:0 are
the fractional part and bits 31:16 are the integer part. The range is -3.0 to +3.999 high-rate samples.
The phase compensation registers are PhComp A, PhComp B, and PhComp C.
2.3.7 Limit (Alarms) Settings
The Limit registers set limits on result values causing Status Register bits to be set when a limit
threshold is exceeded. Limit registers use the same scaling applied to results and, as such, are user-
definable.
Sticky Bits
The user has the option to choose which Status Register bits will clear automatically once an alarm
condition no longer exists. Each bit in the Sticky Register corresponds to the same bit in the Status
Register. When a Sticky bit is set, the same bit in the Status register will not clear automatically.
They can only be cleared by writing the Status Register.
2.3.8 Creep Threshold
The 78M6631 includes a “no-load” detection feature that eliminates what is commonly referred as “meter
creep.” Meter creep is defined as power (or energy) that is read by the system when there is no load
attached. The FW sets the current to zero reading when its value falls below the programmable threshold.
2.3.9 Digital I/O Configuration
Five digital I/Os (DIOs) can be controlled by the user through the serial communication interfaces. These
digital I/Os are set as output and their logic levels are controlled through MASK registers. See Section
5.4.4 .