Maxim Integrated 78M6610+PSU Hardware Design Guidelines - Manual (Page 14)

78M6610+PSU Hardware Design Guidelines AN_6610_107
14 Rev 0
5 Printed Circuit Board Layout Guidelines
The 78M6610+PSU minimizes the external component count and reduces the complexity of the printed
circuit board layout design. However, some elements of the board design require consideration for
optimum measurement accuracy and reliability. This section discusses these topics for the Maxim device:
• Printed Circuit Board Stack-up
• Crystal Oscillator Components
• LINE Voltage Resistor Network
• Shunt Current Sensor
• V
3P3
Decoupling Capacitors
• System Communication Interface
This application note does not discuss creepage and clearance requirements described in UL 60950-1.
5.1 Printed Circuit Board Stack-up
The 78M6610+PSU can achieve excellent measurement accuracy using a 2-layer printed circuit board. If
the component density becomes too high resulting in insufficient plane flooding surface area, a 4-layer
stack-up must be employed. The plane flooding surface area is insufficient when the critical components
presented in this application note are not properly shielded and isolated from external noise or each
other. Additionally, there must be multiple redundant connection paths across the board’s surface area to
present low impedance paths for the various power and ground connections. The power and ground
planes should mirror each other as much as possible since the ground return current tends to travel
directly beneath the supply current across the board. This minimizes current loops and radiated
emissions.
The following section regarding the respective critical components uses the 78M6610+PSU Evaluation
Board as an example. The board has a 2-layer plane assignment.