Maxim Integrated 78M6610+PSU Hardware Design Guidelines - Manual (Page 9)

AN_6610_107 78M6610+PSU Hardware Design Guidelines
Rev. 0 9
4 Device Configuration
The following section covers the rest of the hardware interfaces found on the 78M6610+PSU.
4.1 VDC Supply (V
3P3D
, V
3P3A
) and Decoupling
The 78M6610+PSU requires a single 3.3VDC supply. In order to minimize the effect of digital output
switching on the analog circuitry, the 78M6610+PSU has separate supply pins for analog (V
3P3A
/GNDA)
and digital circuitry (V
3P3D
/GNDD). The two supply inputs can be tied to a common voltage node
externally. A ferrite bead connecting the two power domains is not typically needed.
As in every design, particular attention must be paid to the supply voltage ripple noise and proper
decoupling must be provided. Minimizing power supply noise is necessary for reliable operation of the
processors and the various peripherals.
The 78M6610+PSU supply ranges (for both V
3P3A
and V
3P3D
) from 3.0V to 3.6V (or 3.3VDC +/-9%).
These limits include both the DC supply voltage error and the peak amplitude of any noise. Therefore it is
necessary to account for deviation in the regulator output voltage and reduce the peak noise voltage. For
example, given a voltage regulator precision of ±2.5%, the peak noise should never exceed ±2.1 V.
The 78M6610+PSU provides a high PSRR (Power Supply Ripple Rejection). However, it is necessary to
limit the ripple and its frequency components. It is preferable to limit the ripple amplitude to 100 mV (pk-
pk) and its frequency components to100 KHz. In these conditions the effect of the ripple noise on the A/D
Converter accuracy, clock jitter and other peripherals is greatly minimized.
Voltage regulators have a tolerance typically between 1% and 2.5%. The voltage regulator output and the
noise component should not exceed the 3.6 V to 3.0 V supply range (see Figure 5).
3.600
3.300
3.000
Ripple (100 mV – Max)
SUPPLY OUT OF RANGE
SUPPLY OUT OF RANGE
Figure 5: Supply Range