ADLINK DAQe-2006 - Manual (Page 86)

74 Operation Theory
The six internal timing signals could be routed to the SSI or the
PXI trigger bus through software drivers. Refer to section 4.6 for
detailed information on the six internal timing signals. Physically
the signal routings are accomplished in the FPGA. Cards that are
connected together through the SSI or the PXI trigger bus, will still
achieve synchronization on the six timing signals.
The mechanism of the SSI/PXI
X We adopt master-slave configuration for SSI/PXI. In a sys-
tem, for each timing signal, there shall be only one master,
and other cards are SSI slaves or with the SSI function dis-
abled.
X For each timing signal, the SSI master does not have to be
in a single card.
For example:
We want to synchronize the A/D operation through the ADCONV
signal for four DAQ-/DAQe-/PXI-2016/2010/2006/2005 cards.
Card 1 is the master, and Card 2, 3, 4 are slaves. Card 1 receives
an external digital trigger to start the post trigger mode acquisition.
The SSI setting could be:
X Set the SSI_ADCONV signal of Card 1 to be the master.
X Set the SSI_ADCONV signals of Card 2, 3, 4 to be the
slaves.
X Set external digital trigger for Card 1’s A/D operation.
X Set the SI_counter and the post scan counter (PSC) of all
other cards.
X Start DMA operations for all cards, so all the cards are wait-
ing for the trigger event.
When the digital trigger condition of Card 1 occurs, Card 1 will
internally generate the ADCONV signal and output this ADCONV
signal to SSI_ADCONV signal of Card 2, 3 and 4 through the SSI/
PXI connectors. Thus we can achieve 16-channel acquisition
simultaneously.
You could arbitrarily choose each of the six timing signals as the
SSI master from any one of the cards. The SSI master can output
the internal timing signals to the SSI slaves. With the SSI, users
could achieve better card-to-card synchronization.