ADLINK ACL-8112 Series - Manual (Page 30)

22 • Registers
• CN1: Digital Signal Output (DO 0 to 15 )
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
DO 0
DO 2
DO 4
DO 6
DO 8
DO 10
DO 12
DO 14
GND
+5V
DO 1
DO 3
DO 5
DO 7
DO 9
DO 11
DO 13
DO 15
GND
+12V
CN1
Figure 3.2 Pin Assignment of CN1
Note:
DO n:
Digital output signal channel n
DI n: Digital input signal channel n
GND: Digital ground
• CN3: Analog Input/Output & Counter/Timer
(for single-ended connection: ACL-8112DG/HG/PG)
AI2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
30
20
31
32
33
34
35
36
37
AI3
AI1
AI0
AI6
AI7
AI5
AI4
A.GND
A.GND
V.REF
ExtRef2
A.GND
+12V
D.GND
AI10
AI9
AI8
AI13
AI14
AI12
AI11
AO1
A.GND
AI15
A.GND
ExtRef1
AO2
GATE0
GATE
N/C
ExtCLK
N/C
+5V
ExtTrg
COUT0
CN3
N/C
Figure 3.3a Pin Assignment of CN3