ADLINK ACL-8112 Series - Manual (Page 38)

30 • Registers
4.1 I/O Port Address
The ACL-8112 requires 16 consecutive addresses in the PC I/O address
space. Table 4.1 shows the I/O address of each register with respect to the
base address. The function of each register is also listed.
I/O Address Read Write
Base + 0 Counter 0 Counter 0
Base + 1 Counter 1 Counter 1
Base + 2 Counter 2 Counter 2
Base + 3 Not Used 8254 Counter Control
Base + 4 A/D low byte CH1 D/A low byte
Base + 5 A/D high byte CH1 D/A high byte
Base + 6 DI low byte CH2 D/A low byte
Base + 7 DI high byte CH2 D/A high byte
Base + 8 Not Used Clear Interrupt Request
Base + 9 Not Used A/D Range Control
Base + 10 Not Used Channel MUX
Base + 11 Not Used Mode Control
Base + 12 Not Used Software A/D trigger
Base + 13 Not Used DO low byte
Base + 14 Not Used DO high byte
Base + 15 Not Used Not Used
Table 4.1 I/O Address