ADLINK PCIe-7200 - Manual (Page 35)

26 Register Format
put FIFO to DO registers when output of Counter1 goes low
0: Output Counter 1 is disabled
O_FIFO: Output FIFO Enable
1: Output FIFO is enabled (output data is moved from output
FIFO)
0: Output FIFO is disabled
O_TRG: Digital Output Trigger Signal
This bit is used to control the O_TRG output of PCI-7200; the
signal is on CN1 pin 36 of PCI-7200, CN1 pin 26 of cPCI-
7200, CN2 pin 34 of LPCI 7200S when
1: O_TRG 1 goes High (1)
0: O_TRG 1 goes Low (0)
 Digital I/O FIFO Status:
I_OVR: Input data overrun
1: Digital Input FIFO is full (overrun) during input data trans-
fer
0: No input data overrun occurred
Input data overrun occurred, the I_OVR bit is set when input
FIFO is full and there is new input data coming in. This bit
can be cleared by writing “1” to it.
O_UND: Output data FIFO is underrun
1: Output FIFO is empty during output data transfer
0: No output data underrun occurred
Output data underrun, the O_UND bit is set when output
FIFO is empty and the output request for new data, this bit
can be cleared by writing “1” to it.