ADLINK PCIe-7200 - Manual (Page 5)

Table of Contents i
Table of Contents
List of Tables.......................................................................... iii
List of Figures ........................................................................ iv
1 Introduction ........................................................................ 1
1.1 Applications ......................................................................... 1
1.2 Features............................................................................... 2
1.3 Specifications....................................................................... 3
1.4 Software Support ................................................................. 5
Driver Support for Windows ............................................ 5
2 Installation ........................................................................ 11
2.1 Contents ............................................................................ 11
2.2 Unpacking.......................................................................... 12
2.3 Device Installation for Windows Systems .......................... 12
2.4 PCI-7200/cPCI-7200/PCIe-7200 Layout............................ 13
2.5 Hardware Installation Outline............................................. 16
2.6 Connector Pin Assignments .............................................. 17
PCI/PCIe-7200 Pin Assignments .................................. 17
cPCI-7200 Pin Assignments ......................................... 19
2.7 8254 for Timer Pacer Generation ...................................... 20
2.8 Onboard Pull-ups and Terminations on the Digital Inputs . 21
3 Register Format................................................................ 23
3.1 I/O Registers Format ......................................................... 23
3.2 Digital Input Register (BASE + 10) .................................... 23
3.3 Digital Output Register (BASE + 14).................................. 24
3.4 DIO Status & Control Register (BASE + 18)...................... 24
3.5 Interrupt Status & Control Register (BASE + 1C) .............. 27
3.6 8254 Timer Registers (BASE + 0) ..................................... 30
4 Operation Theory ............................................................. 31
4.1 Direct Program Control ...................................................... 31
4.2 Timer Pacer Mode ............................................................. 32
4.3 External Clock Mode.......................................................... 33
4.4 Handshaking...................................................................... 34
4.5 Timing Characteristic ......................................................... 36