ADLINK cPCI-7300 - Manual (Page 37)

Operation Theory
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4.4 Input FIFO and Output FIFO
Due to the data transfer rate between external devices and the
cPCI/PCI-7300A is independent from that between cPCI/PCI-7300A and PCI
bus. Two 16K words FIFO are provided to be I/O buffers.
For digital input operation, data is sampled and transferred to the input FIFO.
When the input FIFO is non-empty, the PCI bridge will automatically transfer
the data from the input FIFO to the system memory in the background when
PCI bus is available.
As the data transfer rate from external device to input FIFO (DI pre-transfer
rate) is lower than that from input FIFO to system memory (DI post-transfer
rate), the input FIFO is usually empty. On the contrary, when DI pre-transfer
rate is h igher than DI post-transfer rate, the FIFO becomes full and the overrun
situation occurs if the data size is larger than the FIFO size, that is 16K
samples. When DI overrun happens, the next input data will lose until the input
FIFO becomes non-full once again. Users can check the overrun status by
using the function _ 7300_GetOverrunStatus.
For digital output operation, data is moved from system memory to the output
FIFO by bus mastering DMA, assume the data transfer rate is DO pre-transfer
rate. Then, the data will be transferred to the external devices periodically as
we configured, assume the transfer rate is DO post-transfer rate. When the DO
pre-transfer rate is higher than the DO post-transfer rate, the DMA transfer
stops as the output FIFO becomes full. On the contrary, if DO pre-transfer rate
is lower than DO post-transfer rate. The underrun situation occurs as the
output FIFO becomes empty. The output data remains when underrun
happens. User can check the underrun status by using the function
_7300_GetUnderrunStatus.
Notes: The max data length should be 16K instead of 32K. Users can send
repetitive pattern of 8-/16-/32-bit width with a length of 16K samples,
because of the FIFO depth is as it is no matter how wide the bus.
Users should remember that the FIFO chip size is 32K bytes with
16-bits width. Therefore, for each bit, the depth is 16K.
If you need more depth of data, the data have to be in the PC memory and
chain the pattern memory circularly, and then do chaining mode DMA
which will generate the desired pattern repetitively.