ADLINK cPCI-7300 - Manual (Page 46)

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• Operation Theory
DIREQ as input data strobe (when Falling Edge Active)
Notes: From the timing diagram of external clock mode, the maximum
frequency can be up to 40MHz. However, users should note that
when the sampling frequency of digital input is higher than the PCI
bus bandwidth (33Mhz), or the bandwidth of chipset (30Mhz typically)
from PCI bus to system memory. Users should check the overrun
status when the DMA block size is larger than 16K samples. If overrun
always happens, users should reduce the DMA block size or slow
down the sampling frequency. For example, the DMA block size
should be smaller than 64K when the external clock is 40Mhz in the
DOS Operation
4.10.3 Digital Input DMA in Handshaking Mode
For digital input, through DI-REQ input signal and DI-ACK output signal, the
digital input can have simple handshaking data transfer.The operations
sequence of digital input with handshaking are listed:
1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.
2. Enable or disable the active terminators.
3. Define the input sampling rate as handshaking mode. Connect the
handshaking signals of the external device to input pin DI-REQ and output
pin DI-ACK.
4. Define the starting mode to be NoWait or WaitTRIG.
5. After digital input data is ready on device side, the peripheral device strobe
data into the cPCI/PCI-7300A by asserting a DIREQ signal,
6. The DIREQ signal caused the PCI-7300A to latch digital input data and
store it into FIFO
7. The PCI-7300A asserts a DIACK signal when it is ready for another input,
the step 5 to step 7 will be repeated again.