ADLINK cPCI-7300 - Manual (Page 49)

Operation Theory
• 41
Notes: The latency time between two DMA transfers is different from the PCI
bus latency time mentioned in the previous section of “Bus
Mastering”. The former means the time difference between two
continuous DMA processes started by the software. And the latter
means the time difference between two continuously hardware DMA
requests on the PCI bus within a DMA process.
4.11 Digital Output Operation Mode
4.11.1 Digital Output DMA in Internal Clock Mode
There are three sources to trigger digital output: 20MHz, 10MHz, and
programmable timer 82C54. There are three counters in 82C54, where the
counter 1 is used timer pacer for digital output. The operations sequence of
digital output with internal clock are listed:
1. Define the input configuration to be 32-bit, 16-bit or 8-bit data width.
2. Enable or disable the active terminators.
3. Define the output timer pacer rate to be 20MHz, 10MHz, or the output
82C54 timer 1. The timer pacer controls the output rate.
4. Define the starting mode to b e NoWait, WaitTRIG, WaitFIFO, or WaitBoth
5. The output data saved in the system memory will be transferred to output
FIFO directly and automatically by bus mastering DMA.
6. The digital output data will be transferred to the external device after a DO
command is issued and DO-TRIG signal is activated.
The operation flow is show as below: