ADLINK ACL-7120A/6 - Manual (Page 19)

Installation
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2.6 Interrupt Settings
To use the interrupt function, a second counter chip (CNT 1) needs to be
installed on the ACL-7120A/3. The additional CNT 1 counter chip is included
with the ACL-7120A/6.
The ACL-7120A offers AT bus interrupt levels (IRQ3-IRQ15), and three
interrupt trigger sources (timer pacer, event, and external). The IRQ level is
set by JP2 and is used to define the interrupt IRQ level. The default setting is
IRQ15.
Note : Ensure that the chosen IRQ level does not conflict with existing
hardware or system settings.
JP2
*
default setting : IRQ15
15
12
11
10
9
7
5
4
3
Figure 2.3
The interrupt trigger source is set by JP3. The default setting is “TME IRQ”
and is shown below:
EXT IRQ: External source to trigger interrupt
EVT IRQ: Event counting to trigger interrupt
TME IRQ: Timer Pacer to trigger interrupt