ADLINK ACL-7120A/6 - Manual (Page 28)

22
• Signal Connections
3.3 Interrupt Trigger Source
The second interval timer/counter 8254 chip on the ACL-7120A is used to
generate sources for interrupts. The block diagram of this chip is illustrated
below (figure 3.3).
Counter 3 of the 8254 is used for event counting, it will accept event signals
from CN5 pin-7 and its output will trigger an interrupt when the count value of
Counter 3 is becomes 0.
Counters 4 and 5 are cascaded together for a timer pacer trigger interrupt. Its
clock source is 4Mhz.
Note : The second internal timer/counter 8254 is installed on the ACL-
7120A/6 only. Without it, the functions above will not work.
Counter 3
Counter 4
Counter 5
CLK3
GATE3
OUT3
CLK4
GATE4
CLK5
GATE5
OUT4
OUT5
4MHz
Oscillator
Vcc Timer Pacer IRQ
8254 Timer/Counter
CN5 Pin-7
EVENT
CN5 Pin-9
GATE3
Event IRQ
External IRQ
CN5 Pin-13
External IRQ
Figure 3.3 Block Diagram of 8254 Timer/Counter
The pacer rate of above configuration is determined by the formula:
pacer rate = 4MHz / (C4 * C5)
The maximum pacer signal rate is 4MHz/1=4Mhz. The minimum signal rate is
4MHz / (65535*65535)—an extremely slow frequency.
To get a pacer rate of 2.5kHz, users can set C1 = 40 and C2 = 40:
2.5KHz = 4Mhz / (40 * 40)