ADLINK PXIS-2670 - Manual (Page 21)

Backplane Overview 13
3.5 Local Bus
The local bus of PXI backplane XBP-3014L is a daisy-chained bus
that connects each peripheral slot with its adjacent peripheral slots
to the left and right. Each local bus is 13 lines wide and can pass
analog signals between modules or provide a high-speed side-
band communication path that does not affect the PXI bandwidth.
In accordance with the PXI specification, the local bus connections
between all slots except slots 1 and 2.
3.6 Trigger Bus
ADLINK PXIS-2670 has PXI trigger bus. Users can use triggers to
synchronize the operation of several different PXI peripheral mod-
ules, or use one module to control carefully timed sequences of
operations performed on other modules in the system. Modules
can pass triggers to one another through trigger bus, allowing pre-
cisely timed responses to asynchronous external events the sys-
tem is monitoring or controlling.
3.7 System Reference Clock
The PXIS-2670 supplies the PXI 10MHz system clock signal
(PXI_CLK10) independently to every peripheral slot. An indepen-
dent buffer (having source impedance matched to the backplane
and a skew of less than 1ns between slots) drives the clock signal
to each peripheral slot. Users can use this common reference
clock signal to synchronize multiple modules in a measurement or
control system or drive PXI_CLK10 from an external source
through the PXI_CLK10_IN pin on the P2 connector of the star
trigger slot.
Users can select the internal or external clock by setting the
jumper JP2.
JP2 Description
Pin 1-2 External clock through the PXI_CLK10_IN on star trigger slot
Pin 2-3 Internal 10MHz system clock PXI_CLK10
Table 3-1: JP2: PXI 10MHz Reference Clock Control