ADLINK PXIS-2630 Series - Manual (Page 19)

Backplane Overview • 13
3.6 Trigger Bus
ADLINK PXIS-2650 series implements the dedicated PXI trigger bus with 8
lines. Users can use these trigger lines to synchronize the operation of
several different PXI peripheral modules, or use one module to control
carefully timed sequences of operations performed on other modules in
the system. Modules can pass triggers to one another through trigger bus,
allowing precisely timed responses to asynchronous external events the
system is monitoring or controlling.
3.7 System Reference Clock
The PXIS-2650 series supplies the PXI 10MHz system clock signal
(PXI_CLK10) independently to every peripheral slot. An independent
buffer (having a source impedance matched to the backplane and a skew
of less than 1ns between slots) drives the clock signal to each peripheral
slot. Users can use this common reference clock signal to synchronize
multiple modules in a measurement or control system or drive PXI_CLK10
from an external source through the PXI_CLK10_IN pin on the P2
connector of the star trigger slot.
Users can select the internal or external clock by setting the jumper JP2
and JP3 in the back of the backplane.
JP2 JP3: PXI Reference Clock Control
JP2 JP3 Pin 1-2 Description
Open JP2
Short JP3
External clock through the
PXI_CLK10_IN
on star trigger slot
Short JP2
Open JP3
(default)
Internal 10MHz system clock
PXI_CLK10