ADLINK PCI-9527 - Manual (Page 38)

26 Operation Theory
PCI-9527 ADLINK Technology Inc.
User’s Manual Copyright 2010
3.2.4 FIFO and DMA Transfer For Analog Input
FIFO
There is only one FIFO implemented on PCI-9527 for analog input
data storage. The FIFO depth is 4096 samples. The 4096 samples
are shared for both AI channels. When user enables only one AI
channel, the 4096-sample-FIFO is used for one channel data stor-
age. When user enables two AI channels, the 4096-sample-FIFO
shares for both channel.
Bus-mastering DMA Data Transfer
PCI bus-mastering DMA is essential for continuous data stream-
ing, as it helps to achieve full potential PCI bus bandwidth, and
also to improve bus efficiency. The bus-mastering controller con-
trols the PCI bus when it becomes the master of which, and the
host CPU is free of burden since data are directly transferred to
the host memory without intervention. Once analog input opera-
tion begins, the DMA returns control of the program. During DMA
transfer, the hardware temporarily stores acquired data in the on-
board AD Data FIFO, and then transfers the data to a user-defined
DMA buffer in the computer.
By using a high-level programming library for high speed DMA
data acquisition, users simply need to assign the sampling period
and the number of conversions into their specified counters. After
the AD trigger condition is met, the data will be transferred to the
system memory by the bus-mastering DMA.
In a multi-user or multi-tasking OS, such as Microsoft Windows,
Linux, and so on, it is difficult to allocate a large continuous mem-
ory block. Therefore, the PCI controller provides DMA transfer with
scatter-gather function to link non-continuous memory blocks into
a linked list so users can transfer large amounts of data without
being limited by memory limitations. In non-scatter-gather mode,
the maximum DMA data transfer size is 2 MB double words (8 MB
bytes); in scatter-gather mode, there is no limitation on DMA data
transfer size except the physical storage capacity of your system.
Users can also link descriptor nodes circularly to achieve a multi-
buffered DMA. Figure 4-6 illustrates a linked list that is comprised
of three DMA descriptors. Each descriptor contains a PCI address,