ADLINK PCI-9527 - Manual (Page 41)

Operation Theory 29
ADLINK Technology Inc. PCI-9527
Copyright 2010 User’s Manual
3.3.2 Output Range and Data Format
The following table illustrates the PCI-9527 idea transfer charac-
teristics of various input codes versus output voltages. The data
format of the PCI-9527 is two’s-complement.
3.3.3 DAC and Analog Output Filter
DAC (Digital-to-Analog Converter)
The DACs on PCI-9527 are two 24-bit delta-sigma DACs. It sepa-
rates the sample rates into four regions between 1KS/s to
216KSps (table 3.3.1). Each region has different bandwidth of
internal digital filter, this will optimize the DA dynamic performance
over all sample rate region. For example, when setting at lower
sample rate, the digital filter bandwidth is lower too. It improves
SNR of output current and release the need for external analog
low pass filter.
The relationship between DAC sample rate and DDS output clock
is as followed
Description Digital Input Code Bipolar Analog Output
Full-scale Range ±10V ±1V ±0.1V
Least significant bit 1.19uV 0.119uV 0.012uV
FSR-1LSB 7FFFFF 9.99999881V 0.999999881V 0.099999988V
Midscale +1LSB 000001 1.19uV 0.119uV 0.012uV
Midscale 000000 0V 0V 0V
Midscale –1LSB FFFFFF -1.19uV -0.119uV -0.012uV
-FSR 800000 -10V -1V -0.1V
Table 3-5: Digital Input Code and Analog Output Range
Update Rate 1K-27KHz 27K-54KHz 54K-108KHz 108K-216KHz
DDS CLK 512K-13.824MHz 6.912M-13.824MHz 6.912M-13.824MHz 13.824M-27.648MHz
Table 3-6: DAC (Digital-to-Analog Converter)