ADLINK Express-IBE2 - Manual (Page 29)

Express-IBE2 Page 29
Signal Pin Description I/O PU/PD Comment
PCI_LOCK# C35 PCI Lock control line, active low. I/O 3.3V PU 8k2 3.3V
PCI_SERR# D33 System Error: SERR# may be pulsed active by any PCI device
that detects a system error condition.
I/O 3.3V PU 8k2 3.3V
PCI_PME# C15 PCI Power Management Event: PCI peripherals drive PME# to
wake system from low-power states S1–S5.
I 3.3VSB
PCI_CLKRUN# D48 Bidirectional pin used to support PCI clock run protocol for
mobile systems.
I/O 3.3V PU 10k 3.3V
PCI_IRQA# PCI_IRQB#
PCI_IRQC# PCI_IRQD# C49
C50
D46
D47 PCI interrupt request lines I 3.3V PU 8k2 3.3V
PCI_CLK D50 PCI 33MHz clock output O 3.3V
PCI_M66EN D49 Module input signal indicates whether an off-Module PCI device
is capable of 66MHz operation. Pulled to GND by Carrier Board
device or by Slot Card if the devices are NOT capable of 66
MHz operation.
If the Module is not capable of supporting 66 MHz PCI
operation, this input may be a no-connect on the Module.
If the Module is capable of supporting 66 MHz PCI operation,
and if this input is held low by the Carrier Board, the Module PCI
interface shall operate at 33 MHz.