ADLINK Hurricane-QM57 - Manual (Page 74)

TME-EPIC-HURQM-R2V9 Revision 2.9 Page 68 of 74
#include <stdio.h>
#include <sys/io.h>
#define GPIOBASE 0x0500
// better read from PCI 0:1F.0 config reg 0x48
static const int GPIO_NR[] = {64, 65, 66, 67, 1, 6, 7, 28}; // PCH GPIO nr for pin 13-20
int main() {
int pin, gpio;
unsigned io_sel, lvl, mask;
if (iopl(3)) {
// request I/O access permission
perror("iopl"); return 1; // whoops! - not run as root?
}
outl(inl(GPIOBASE+0x00)|0x100000C2, GPIOBASE+0x00); // set all functions to GPIO
outl(inl(GPIOBASE+0x40)|0x0000000F, GPIOBASE+0x40);
pin = 13;
// X5 connector pin nr: 13..20
gpio = GPIO_NR[pin-13]; // PCH GPIO nr provided by pin
io_sel = gpio<32 ? GPIOBASE+0x04 : GPIOBASE+0x44; // select direction: 0=out, 1=in
lvl = gpio<32 ? GPIOBASE+0x0C : GPIOBASE+0x48; // level of GPIO pins
mask = 1 << (gpio&31);
// bitmask to target gpio inside 32 bit register
outl(inl(io_sel)|mask, io_sel);
// use as input
printf("X5 pin %d (GPIO %d) == %d\n", pin, gpio, (inl(lvl)&mask) != 0);
outl(inl(io_sel)&~mask, io_sel);
// use as output
outl(inl(lvl)&~mask, lvl); // set to 0
outl(inl(lvl)|mask, lvl); // set to 1
return 0;
}