Echelon LonTal Stack - Manual (Page 45)

LonTalk Stack Developer’s Guide 33
The RESET~ Pin
The Echelon Smart Transceiver and Neuron Chip have no special requirements
for the RESET~ (or RST~) pin. See the FT 3120 / FT 3150 Echelon Smart
Transceiver Data Book, the PL 3120 / PL 3150 / PL 3170 Power Line Echelon
Smart Transceiver Data Book, or the Series 5000 Chip Data Book for information
about the requirements for this pin.
However, because a LonTalk Stack device uses two processor chips, the Echelon
Smart Transceiver or Neuron Chip and the host processor, you have an
additional consideration for the RESET~ pin: Whether to connect the host
processor’s reset pin to the Echelon Smart Transceiver or Neuron Chip RESET~
pin.
For most LonTalk Stack devices, you should not connect the two reset pins to
each other. It is usually better for the Echelon Smart Transceiver or Neuron
Chip and the host application to be able to reset independently. For example,
when the Echelon Smart Transceiver or Neuron Chip encounters an error that
causes a reset, it logs the reset cause (see Querying the Error Log); if the host
processor resets the Echelon Smart Transceiver or Neuron Chip directly, possibly
before the Echelon Smart Transceiver or Neuron Chip can detect and log the
error, your application cannot query the Echelon Smart Transceiver or Neuron
Chip error log after the reset to identify the problem that caused the reset. The
Echelon Smart Transceiver or Neuron Chip also resets as part of the normal
process of integrating the device within a network; there is normally no need for
the host application to reset at the same time.
In addition, the host processor should not reset the Echelon Smart Transceiver or
Neuron Chip while it is starting up (that is, before it sends the
LonResetNotification uplink reset message to the host processor).
For devices that require the host application to be able to control all operating
parameters of the Echelon Smart Transceiver or Neuron Chip, including reset,
you can connect one of the host processor’s general-purpose I/O (GPIO) output
pins to the Echelon Smart Transceiver or Neuron Chip RESET~ pin, and drive
the GPIO pin to cause an Echelon Smart Transceiver or Neuron Chip reset from
within your application or within your serial driver. Alternatively, you can
connect one of the host processor’s GPIO input pins to the Echelon Smart
Transceiver or Neuron Chip RESET~ pin so that the host application can be
informed of Echelon Smart Transceiver or Neuron Chip resets.
A host processor’s GPIO output pin should not actively drive the Echelon Smart
Transceiver’s RESET~ pin high, but instead should drive the pin low. You can
use one of the following methods to ensure that the GPIO pin cannot drive the
RESET~ pin high:
• Ensure that the GPIO pin is configured as an open-drain (open-collector)
output
• Ensure that the GPIO pin is configured as a tri-state output
• Place a Schottky diode between the GPIO pin and the RESET~ pin, with
the cathode end of the diode connected to the GPIO pin
Configuring the GPIO pin as either open drain or tri-state ensures that the GPIO
pin is in a high-impedance state until it is driven low. Using a Schottky diode is
preferable to using a regular diode because a Schottky diode has a low forward
voltage drop (typically, 0.15 to 0.45 V), whereas a regular diode has a much