Echelon LonTal Stack - Manual (Page 48)

36 Designing the Serial I/O Hardware Interface
Host Latency Considerations
The processing time required by the host processor for an Echelon Smart
Transceiver or Neuron Chip can have a significant impact on link-layer transit
time for network communications and on the total duration of network
transactions. This impact is the host latency for the LonTalk Stack application.
To maintain consistent network throughput, a host processor must complete each
transaction as quickly as possible. Operations that take a long time to complete,
such as flash memory writes, should be deferred whenever possible. For
example, an ARM7 host processor running at 20 MHz can respond to a
network-variable fetch request in less than 60 µs, but typically requires 10-12 ms
to erase and write a sector in flash memory.
The following formula shows the overall impact of host latency on total
transaction time:
( ) ( )
host linklayer r MicroServe channel trans
t t t t t
+ + + = * 2
where:
•
trans
t is the total transaction time
•
channel
t is the channel propagation time
•
r MicroServe
t is the Echelon Smart Transceiver or Neuron Chip latency
(approximately 1 ms for a Series 3100 Echelon Smart Transceiver
running at 10 MHz; approximately 65 µs for a FT 5000 Echelon Smart
Transceiver running with an 80 MHz system clock)
•
linklayer
t is the link-layer transit time
•
host
t is the host latency
The channel propagation time and the Echelon Smart Transceiver latency are
fairly constant for each transaction. However, link-layer transit time and host
latency can be variable, depending on the design of the host application.
You must ensure that the total transaction time for any transaction is much less
than the L ON W ORKS network transmit timer. For example, the typical transmit
timer for a TP/FT-10 channel is 64 ms, and the transmit timer for a PL-20
channel is 384 ms.
Typical host processors are fast enough to minimize link-layer transit time and
host latency, and to ensure that the total transaction time is sufficiently low.
Nonetheless, your application might benefit from using an asynchronous design
of the host serial driver and from deferring time-consuming operations such as
flash memory writes.
SCI Interface
The LonTalk Stack Serial Communications Interface (SCI) is an asynchronous
serial interface between the Echelon Smart Transceiver or Neuron Chip and the
host processor. The communications format is:
• 1 start bit