Altera MAX 10 Clocking and PLL - Manual (Page 34)

The counter settings are updated synchronously to the clock frequency of the individual counters.
Therefore, not all counters update simultaneously.
The dynamic reconfiguration scheme uses configuration files, such as the Hexadecimal-format file (.hex)
or the Memory Initialization file (.mif). These files are used together with the ALTPLL_RECONFIG IP
core to perform the dynamic reconfiguration.
Related Information
• Guideline: .mif Streaming in PLL Reconfiguration on page 3-4
• PLL Dynamic Reconfiguration Implementation on page 4-10
• PLL Dynamic Reconfiguration Parameter Settings on page 6-4
Provides more information about the ALTPLL IP core parameter settings in the Quartus II software.
• ALTPLL_RECONFIG Parameters on page 7-1
Provides more information about the ALTPLL_RECONFIG IP core parameter settings in the Quartus
II software.
2-28 PLL Reconfiguration
UG-M10CLKPLL
2015.05.04
Altera Corporation MAX 10 Clocking and PLL Architecture and Features
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