Altera Embedded Peripherals IP - Manual (Page 147)

#---------------- Do NOT change ------------------------------- ---- Change -----
array set map_user_pin_name_to_internal_pin_name {ad ad }
b. Edit the pin names under the
Change
header in the file to match the PCI pin names used in your
Quartus II project. In the following example, the name
ad
is changed to
pci_ad
:
#---------------- Do NOT change ------------------------------- ---- Change -----
array set map_user_pin_name_to_internal_pin_name { ad pci_ad }
Note: The Tcl constraint file uses the default PCI pin names to make assignments. When overwriting
existing assignments, the Tcl constraint file checks the new assignment pin names against the
default PCI pin names. You must update the assignment pin names if there is a mismatch between
the assignment pin names and the default PCI pin names.
1. Source the constraint file by typing the following in the Quartus II Tcl Console window:
source pci_constraints.tcl
r
2. Add the PCI constraints to your project by typing the following command in the Quartus II Tcl
Console window:
add_pci_constraints
r
See Additional Tcl Option section for the option supported by the add_pci_constraints
command.
When you add the timing constraints file as described in Step 4 above, the Quartus II software
generates a Synopsys Design Constraints ( .sdc ) file with the file name format, <variation
name>.sdc. The Quartus II TimeQuest timing analyzer uses the constraints specified in this file.
For more information about .sdc files or TimeQuest timing analyzer, refer to Quartus II Help.
Additional Tcl Option
If you do not want to compile your project and prefer to skip analysis and synthesis, you can use
the
-no_compile
option:
add_pci_contraints [-no_compile]
By default, the
add_pci_constraints
command performs analysis and synthesis in the
Quartus II software to determine the hierarchy of your PCI Lite core design. You should only
use this option if you have already performed analysis and synthesis or fully compiled your
project prior to using this script.
Simulation Considerations
The PCI Lite core includes a testbench that facilitates the design and verification of systems that
implement the Altera PCI-Avalon bridge. The testbench only works for master systems and is provided in
Verilog HDL only.
To use the PCI testbench, you must have a basic understanding of PCI bus architecture and
operations.This section describes the features and applications of the PCI testbench to help you success‐
fully design and verify your design.
Features
UG-01085
2014.24.07
Simulation Considerations 14-13
PCI Lite Core Altera Corporation
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